Unpacked/packed type assignment

SystemVerilog
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1

Hi,

I have another question for you guys. I declared an unsigned dynamic array of bytes (therefore unpacked?!) which looks like this:

byte unsigned dchar_req [];

The dchar_req array shall be able to increase in size, whenever a new byte is available (a byte container if you like).
Inside a task, I have a queue (so another unpacked array) that contains 9 bits at a certain point.

Declaration and initialization:

logic actual_char_tx [$:8] = '{1,1,1,1,1,1,1,1,1};

At the mentioned point, I want to add a slice of the current content of actual_char_tx, i.e. the 8 right most bits, so actual_char_tx[1:8] as a byte
to the dynamic array.

dchar_req = new[dchar_req.size()+1](dchar_req);      // Preserve previous array contents
dchar_req[dchar_req.size()-1] = actual_char_tx[1:8]; // Add queue slice to the resized dynamic array

The compiler output is as follows:

“Case item comparison: Cannot assign an unpacked type ‘reg []’ to a packed type ‘byte unsigned’.”

I’m confused about dchar_req being identified as a packed type although by declaration it is unpacked?!

2

In reply to Fipser@VA:
dchar_req is an unpacked array of a packed array. You are trying to make an assignment to one element of the unpacked array, which is a byte. byte unsigned is equivalent to the packed array bit [7:0].
You can replace your two lines with an unpacked array concatenation:

dchar_req = { dchar_req, byte'(actual_char_tx[1:8]) };
3

In reply to dave_59:

In reply to Fipser@VA:
byte unsigned is equivalent to the packed array bit [7:0].

This means

byte unsigned dchar_req [];

is equivalent to the mixed packed/unpacked(dynamic) array

bit [7:0] dchar_req [];

?.

4

In reply to Fipser@VA:

yes. unpacked array of a packed array.

5

Thanks!