Difference between packed and unpacked arrays?

SystemVerilog
,
1

hi, I have a big confusion in packed and unpacked arrays.
can anyone tel me the difference between the below 2.
logic [3:0]m[5:0]; and
logic [3:0][5:0]m;
here in first m is unpacked array of size 6 with each element is packed of 4 bits ?

2

In reply to pawar:

https://verificationacademy.com/forums/ovm/difference-between-packed-and-unpacked-arrays