Packed array to struct

SystemVerilog
,
1

I am trying to get some values to struct based on a packed array. It seems rsp.addr when it gets value from packed array p_data[1][11:4] which i expect it to be 'hbc. It seems 2/3 simulators give the correct results. any problem with the below code?



module tb;
  typedef struct packed {
    logic bs; //31
    logic [2:0] ecc;// 28
    logic [7:0] addr; //20-27
    logic [15:0] data;// 4-19
    logic [3:0] par; // 0-3
  
  } req_s;
  
  req_s req,rsp;
  bit[1:0][17:0] p_data;
  
  initial begin
    req = 32'habcdefab;
    p_data[0] = 18'h1efab;
    p_data[1] = 18'h1abcd; // 01_1010_1011_1100_1101
    $displayh("struct=%p",req);
    {>>{rsp.addr}} = p_data[1][11:4];
    $display("rsp = %p",rsp);
  end
  // 01_1000_1000
endmodule
2

In reply to rag123:

All 4 simulators on EDAPlayground give the same results for rsp.addr, 'hbc (Except one does not support %p on a struct).

There is no need for streaming operator here as both LHS and RHS are packed.