Array randomization

SystemVerilog
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1

Hi,

In the below piece of code, Why can’t an array be randomized as shown below. What is wrong in the below piece of code?


class sv_arrays;
  rand int [1:0] arr [5];
endclass

module top;
  initial begin
    sv_arrays arr_inst;
    arr_inst = new();
    arr_inst.randomize();
    $display ("array=0x%0x\n", arr_inst.arr);
  end
endmodule
2

In reply to vinodrm:

The problem is not with randomization. You are not allowed to declare a packed array of an int/integer/shortint/longint/byte type. There are two reason for this.

In most other programming languages, these types do not have fixed sizes; they are platform dependent. So packing them would create un-portable types. (SystemVerilog has since fixed the sizes of all integral types.

The other reason was an unimplemented feature of Verilog that was going to allow you to declare a fixed size integer using integer [15:0] A; instead of shortint A, but most Verilog simulators just ignored the syntax.

So if you need a packed array of int, you need to declare it as

bit signed [1:0][31:0] A;

Finally, there is no %x format in SystemVerilog. And to display an array in hex use

$displayh("array=%p",arr_inst.arr);
3

In reply to dave_59:

Finally, there is no %x format in SystemVerilog.

Section 21.2.1.2 Format specifications states that either %x or %h display the value in hex format. This works for integral values.

I think what you meant is that there isn’t any hex format specifier that works on complete arrays.