In reply to vinodrm:
The problem is not with randomization. You are not allowed to declare a packed array of an int/integer/shortint/longint/byte type. There are two reason for this.
In most other programming languages, these types do not have fixed sizes; they are platform dependent. So packing them would create un-portable types. (SystemVerilog has since fixed the sizes of all integral types.
The other reason was an unimplemented feature of Verilog that was going to allow you to declare a fixed size integer using integer [15:0] A; instead of shortint A, but most Verilog simulators just ignored the syntax.
So if you need a packed array of int, you need to declare it as
bit signed [1:0][31:0] A;
Finally, there is no %x format in SystemVerilog. And to display an array in hex use
$displayh("array=%p",arr_inst.arr);