Randomizing packed array

SystemVerilog
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1

Hi All,

Can someone help me to understand the basic concept of how packed array slicing works?
what i want to do is
i have an array lets say,
logic [100:0] A;
i want to slice A into particular set of bits lets say 10 bit makes one element, like this i have total 10 elements in A.
out of which few of them are supposed to value as all ones; (as one 10 bit value)
so basically out of 10 elements in “A” i want to set few 10bit wide elements as 'h3FF. that number is a randomly generated number and i want to generate random pattern in A.

thanks
one way i can think of is slice it down in 10 different elements and select randomly to which one i want to set it all 1’s.

2

In reply to Blitzz0418:

There are a couple of ways of approaching this depending on how you want to constrain the number of elements that have all ones set, and what you want the elements that do not have all ones.

class myclass;
  rand bit [99:0] A; // assumes you wanted an exact multiple of 10
    constraint all_ones { foreach (A[i]) 
      i % 10 == 0 -> A[i+:10] == '1 dist {1:=25,0:=75}; //25% 
                        }
endclass

class myclass;
  rand bit [9:0][9:0] A; // 2-D packed array
    constraint all_ones { foreach (A[i]) 
      A[i] == '1 dist {1:=25,0:=75}; //25% 
                        }
endclass
3

In reply to dave_59:

Dave , is the '1 treated as unsigned OR signed ?

Since it doesn’t have size associated with it , I assume it could be interpreted
as Signed .

An Application of what I mean to ask ::

Consider a constraint expression with signed variables .

If I were to write '1 in that expression will the overall expression be treated
as signed OR unsigned ?

4

In reply to ABD_91:

It’s not super clear in the LRM, but’s treated as unsigned.

5

In reply to dave_59:
Hi dave ,
can you tell me what does " A[i+:10] " mean?? particularly i+:10.
thanks

6

In reply to Blitzz0418:

See Range must be bounded by constant expressions | Verification Academy