Verification Academy
Randomizing packed array
SystemVerilog
array-slicing
,
systemverilog-Arrays-packedarrays-unpackedarrays
,
SV-systemVerilog-constraints-array
,
systemverilog-Arrays
,
systemverilog-arrays-struct-constraint-randomization-indexes
,
SystemVerilog
dave_59
April 23, 2021, 8:17pm
4
In reply to
ABD_91
:
It’s not super clear in the LRM, but’s treated as unsigned.
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