Topics tagged systemverilog-arrays-struct-constraint-randomization-indexes

Topic	Replies	Views	Activity
System Verilog interview question SystemVerilog SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays , systemverilog-arrays-struct-constraint-randomization-indexes	5	1809	June 29, 2024
Constraint to randomize elements of an array such that at least one is a multiple of 4 UVM UVM , constraint-randomization , systemverilog-arrays-struct-constraint-randomization-indexes	1	456	December 3, 2023
Constraint Randomization question SystemVerilog SystemVerilog , constraint-randomization , systemverilog-Arrays-packedarrays-unpackedarrays , systemverilog-arrays-struct-constraint-randomization-indexes	8	4470	June 8, 2023
Generate NXN Matrix with following rules SystemVerilog SystemVerilog , systemverilog-Arrays , systemverilog-arrays-struct-constraint-randomization-indexes , square-matrix , constraint-dynamic	2	571	April 26, 2023
Constraint for region SystemVerilog SystemVerilog , systemverilog-arrays-struct-constraint-randomization-indexes	1	578	October 29, 2021
SV questions for interviews - any additional answers are appreciated SystemVerilog SystemVerilog , constraint-randomization , systemverilog-Arrays-packedarrays-unpackedarrays , systemverilog-arrays-struct-constraint-randomization-indexes , system-verilog-assertions-past-stable	1	1478	October 22, 2021
Assertion interpretation for `true, x=0 ##0 (!a[0:$] ##1 a, x=x+data)[4] ##1 b ##1 c && (data_out==x); SystemVerilog SystemVerilog , assertion , systemverilog-arrays-struct-constraint-randomization-indexes	1	686	October 15, 2021
Significance of {$random} SystemVerilog SystemVerilog , random , systemverilog-arrays-struct-constraint-randomization-indexes	3	1015	August 12, 2021
Constraint randomization for two address regions SystemVerilog SystemVerilog , constraint-randomization , systemverilog-Arrays , systemverilog-arrays-struct-constraint-randomization-indexes	3	1329	August 5, 2021
For Serial protocol, Why need data field in dynamic array or queue instead of normal vector in transaction class? SystemVerilog SystemVerilog , transaction-class , Queue-decleration-in-transaction-class , queues-systemverilog , systemverilog-arrays-struct-constraint-randomization-indexes	0	598	July 10, 2021
Constraint number of occurrences in dynamic array SystemVerilog SystemVerilog , Assertion-system-verilog , systemverilog-constraint , systemverilog-arrays-struct-constraint-randomization-indexes , mdarray-constraint-foreachconstraint-arrayliteral	4	2609	May 18, 2021
Randomizing packed array SystemVerilog SystemVerilog , array-slicing , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays , SV-systemVerilog-constraints-array , systemverilog-arrays-struct-constraint-randomization-indexes	5	1463	May 8, 2021
How to pass struct from one class to another SystemVerilog SystemVerilog , systemverilog-arrays-struct-constraint-randomization-indexes	1	889	April 3, 2021
I want to constrained random 10 bit such that there won't be 7 consecutive 0s or 1s. Can someone suggest anything ? Thanks in advance SystemVerilog SystemVerilog , systemverilog-arrays-struct-constraint-randomization-indexes	3	853	February 13, 2021
Constraint dynamic array SystemVerilog SystemVerilog , systemverilog-arrays-struct-constraint-randomization-indexes	3	1251	September 20, 2020
How to assign values to struct inside another struct SystemVerilog SystemVerilog , typedef , systemverilog-arrays-struct-constraint-randomization-indexes	3	3443	September 15, 2020
Inline constraint while using uvm_do_on_with SystemVerilog SystemVerilog , UVM , systemverilog-uvm , systemverilog-constraint , systemverilog-arrays-struct-constraint-randomization-indexes	6	2964	August 29, 2020
Constraint a 9x9 matrix SystemVerilog SystemVerilog , systemverilog-arrays-struct-constraint-randomization-indexes	14	2702	August 23, 2020
Sum the array values SystemVerilog SystemVerilog , systemverilog-Arrays , systemverilog-arrays-struct-constraint-randomization-indexes	9	1711	May 19, 2020
Struct in System verilog SystemVerilog SystemVerilog , systemverilog-arrays-struct-constraint-randomization-indexes	8	4123	May 18, 2020

System Verilog interview question

SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays , systemverilog-arrays-struct-constraint-randomization-indexes

5

1809

June 29, 2024

Constraint to randomize elements of an array such that at least one is a multiple of 4

UVM

UVM , constraint-randomization , systemverilog-arrays-struct-constraint-randomization-indexes

1

456

December 3, 2023

Constraint Randomization question

SystemVerilog

SystemVerilog , constraint-randomization , systemverilog-Arrays-packedarrays-unpackedarrays , systemverilog-arrays-struct-constraint-randomization-indexes

8

4470

June 8, 2023

Generate NXN Matrix with following rules

SystemVerilog

SystemVerilog , systemverilog-Arrays , systemverilog-arrays-struct-constraint-randomization-indexes , square-matrix , constraint-dynamic

2

571

April 26, 2023

Constraint for region

SystemVerilog

SystemVerilog , systemverilog-arrays-struct-constraint-randomization-indexes

1

578

October 29, 2021

SV questions for interviews - any additional answers are appreciated

SystemVerilog

SystemVerilog , constraint-randomization , systemverilog-Arrays-packedarrays-unpackedarrays , systemverilog-arrays-struct-constraint-randomization-indexes , system-verilog-assertions-past-stable

1

1478

October 22, 2021

Assertion interpretation for `true, x=0 ##0 (!a[*0:$] ##1 a, x=x+data)[*4] ##1 b ##1 c && (data_out==x);

SystemVerilog

SystemVerilog , assertion , systemverilog-arrays-struct-constraint-randomization-indexes

1

686

October 15, 2021

Significance of {$random}

SystemVerilog

SystemVerilog , random , systemverilog-arrays-struct-constraint-randomization-indexes

3

1015

August 12, 2021

Constraint randomization for two address regions

SystemVerilog

SystemVerilog , constraint-randomization , systemverilog-Arrays , systemverilog-arrays-struct-constraint-randomization-indexes

3

1329

August 5, 2021

For Serial protocol, Why need data field in dynamic array or queue instead of normal vector in transaction class?

SystemVerilog

SystemVerilog , transaction-class , Queue-decleration-in-transaction-class , queues-systemverilog , systemverilog-arrays-struct-constraint-randomization-indexes

0

598

July 10, 2021

Constraint number of occurrences in dynamic array

SystemVerilog

SystemVerilog , Assertion-system-verilog , systemverilog-constraint , systemverilog-arrays-struct-constraint-randomization-indexes , mdarray-constraint-foreachconstraint-arrayliteral

4

2609

May 18, 2021

Randomizing packed array

SystemVerilog

SystemVerilog , array-slicing , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays , SV-systemVerilog-constraints-array , systemverilog-arrays-struct-constraint-randomization-indexes