Inline constraint while using uvm_do_on_with

SystemVerilog
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1

I have below code in my virtual sequencer, except the data array inline constraint(shown below as commented at present in READ transaction), everything works well, if I take off the data constraint in the READ transaction below, it works well.

class my_sequence;
      axi_base_seq         axi_wseq;
      axi_base_seq         axi_rseq;
      axi_master_sequencer axi_seqr;
      axi_seqr = uvm_test_top.env_h.axi_agent.seqr;

  `uvm_do_on_with(axi_wseq, axi_seqr, 
  {
    s_kind == axi_type_pkg::WRITE;
    s_id inside {[axi_seqr.cfg_h.id_lo:axi_seqr.cfg_h.id_hi]};
    s_addr == 'haaaaaaa;
    s_length inside {[1:15]};
    s_size inside {[1:4]};
    s_wait_for_rsp == 1;
  })

  `uvm_do_on_with(axi_rseq, axi_seqr, 
  {
    s_kind == axi_type_pkg::READ;
    s_id == axi_wseq.req.id;
    s_addr == axi_wseq.req.addr;
    s_length == axi_wseq.req.length;
    s_size == axi_wseq.req.size;
    s_burst == axi_wseq.req.burst;
    s_wait_for_rsp == axi_wseq.req.wait_for_rsp;
    //##foreach(axi_wseq.req.data[k]) s_data[k] == axi_wseq.req.data[k]; //I need this for score boarding purpose, so this is my question??? please share the answer for this line.
  })

This is the base sequence I am using,

class axi_base_seq extends uvm_sequence #(axi_seq_item);
  string tID;

  rand axi_type_pkg::eAxiKind s_kind;
  rand bit [8:0] s_id;
  rand bit [31:0] s_addr;
  rand bit [255:0] s_data[];
  rand bit [4:0] s_length;
  rand bit [2:0] s_size;
  rand bit [3:0] s_qos;
  rand bit [5:0] s_user;
  rand eAxiBurstKind s_burst;
  rand bit s_wait_for_rsp;

  task body();
    req = axi_seq_item::type_id::create("req");
    `uvm_info(tID,$sformatf("sequence RUNNING id=%x addr=0x%0x length=%d", s_id, s_addr, s_length),UVM_DEBUG)
    `uvm_do_with(req, {
      req.addr == s_addr;
      req.length == s_length;
      req.size == s_size;
      req.burst == s_burst;
      req.id == s_id;
      req.kind == s_kind;
      req.addr == s_addr;
      req.wait_for_rsp == s_wait_for_rsp;
      foreach(s_data[i]) req.data[i] == s_data[i];
    })

    `uvm_info(tID,$sformatf("sequence COMPLETE id=%x", s_id), UVM_DEBUG)    
  endtask : body

This is my sequence item and its constraint,

class axi_seq_item_base  extends uvm_sequence_item; 

  rand eAxiKind kind;
  rand bit [8:0] id;
  rand bit [32:0] addr;
  rand bit [255:0] data []; 
  rand bit [4:0] length;
  rand bit [2:0] size;
  rand bit [3:0] qos;
  rand bit [5:0] user;
  rand eAxiBurstKind burst;
  rand eAxiRspKind resp;
  rand bit wait_for_rsp;

  constraint c_data_array { 
    data.size() == length+1; 
  }

  constraint c_max_length { length < 16; }
  constraint c_align { addr % 2**size == 0; }
  constraint c_burst { burst inside {axi_type_pkg::FIXED, axi_type_pkg::INCR,axi_type_pkg::WRAP};}
  constraint wrap_lenght {if (burst == axi_type_pkg::WRAP) length inside {1,3,7,15};}
  
  constraint c_dj_bytes {if (burst == axi_type_pkg::WRAP) {2**size *(length+1) == 64};}
  constraint c_dj_alow  {if (burst == axi_type_pkg::WRAP) {addr[4:0] == 0};}
  constraint c_dj_user  {if (burst == axi_type_pkg::WRAP) {addr[11:6] == user[5:0]};}
  //constraint c_dj_bit5  {if (burst == axi_type_pkg::WRAP) {addr[5] == !addr[5]};}

Why my randomization fails when I try to keep the inline constraint for the data array?

I start my_sequence from my top_test class with null sequencer, as I use sequencer as shown above for the axi item, which using uvm_do_on_with.

This is the error message —>> This constraint was not processed due to: array index out of bounds The array involved is: rand bit [255:0] s_data; (from the base sequence shown above)

As I shown above , if I remove this array constraint line, ultimately both arrays from axi_wseq and axi_rseq have the same length(that is because axi_rseq length is also assigned with axi_wseq and randomization go well) but different data.

Thank you and best regards.

2

In reply to megamind:

I would recommend not using the `uvm_do_* macros. These add a layer of complexity which make things difficult to debug. Instead, use the start_item()/randomize()/finish_item() methodology.

Additionally, if you are assigning every element of your transaction to a known value, why call randomize? I would skip calling randomize() and just assign the values required.

3

In reply to cgales:

Thank you.

Please let me clarify the example I showed was for just explanation, WRITE transaction need to be completely random but the READ transaction should match with WRITE transaction, so READ transaction should be directed with WRITE transaction values, and for a reason it is not taking those directed values!!! which I want to know how can be best handled.

>>I would recommend not using the `uvm_do_ macros. These add a layer of complexity which make things difficult to debug. Instead, use the start_item()/randomize()/finish_item() methodology.*
I can try this, if this is the cause of the failure.

>>Additionally, if you are assigning every element of your transaction to a known value, why call randomize? I would skip calling randomize() and just assign the values required.
How can I do that here in this context? can you please show syntax for example instead of,

`uvm_do_on_with(axi_rseq, axi_seqr, 
  {
    s_kind == axi_type_pkg::READ;
    s_id == axi_wseq.req.id;
    s_addr == axi_wseq.req.addr;
    s_length == axi_wseq.req.length;
    s_size == axi_wseq.req.size;
    s_burst == axi_wseq.req.burst;
    s_wait_for_rsp == axi_wseq.req.wait_for_rsp;
    //##foreach(axi_wseq.req.data[k]) s_data[k] == axi_wseq.req.data[k]; //I need this for score boarding purpose, so this is my question??? please share the answer for this line.
  })

What should be replaced?

4

In reply to megamind:

You can read about the sequence/sequencer flow at this UVM Cookbook page.

Instead of calling randomize(), you can just assign your fields:


  task body();
    req = axi_seq_item::type_id::create("req");
    `uvm_info(tID,$sformatf("sequence RUNNING id=%x addr=0x%0x length=%d", s_id, s_addr, s_length),UVM_DEBUG)
    start_item(req);
    req.addr == s_addr;
    req.length == s_length;
    req.size == s_size;
    req.burst == s_burst;
    req.id == s_id;
    req.kind == s_kind;
    req.addr == s_addr;
    req.wait_for_rsp == s_wait_for_rsp;
    foreach(s_data[i]) req.data[i] == s_data[i];
    finish_item(req);
    `uvm_info(tID,$sformatf("sequence COMPLETE id=%x", s_id), UVM_DEBUG)    
  endtask : body
5

In reply to cgales:

Thank you, I have updated your syntax recommendation inside my base sequence “class axi_base_seq”, as you suggested, but that did not solve the issue. Also “class my_sequence” is a virtual sequence, which I am starting in my top test, so later in the my_sequence, I am using uvm_do_on_with, as I need to pass some sequencer.

However I could solve my problem with below change in the “class my_sequence”

  `uvm_do_on_with(axi_rseq, axi_seqr, 
  {
    s_kind == axi_type_pkg::READ;
    s_id == axi_wseq.req.id;
    s_addr == axi_wseq.req.addr;
    s_length == axi_wseq.req.length;
    s_size == axi_wseq.req.size;
    s_burst == axi_wseq.req.burst;
    s_wait_for_rsp == axi_wseq.req.wait_for_rsp;
    s_data.size() == axi_wseq.req.data.size();                       //This solved the issue
    foreach(axi_wseq.req.data[k]) s_data[k] == axi_wseq.req.data[k]; //Now this line don't produce any error and randomization works well with uvm_do_on_with
  })

Do you have any further comments? Thank you.

6

In reply to megamind:

If you are starting a sequence from a virtual sequencer, the flow is similar:


  axi_rseq = axi_base_seq::type_id::create("axi_rseq");
  axi_rseq.s_kind == axi_type_pkg::READ;
  axi_rseq.s_id = axi_wseq.id;
  ...
  axi_rseq.start(axi_seqr);
7

In reply to cgales:

Got it, I have made some changes to my sequence item and base sequence as below. Also for the READ where I need directed values from the previous WRITE transaction(for score boarding purpose), I can make changes according your inputs. Your valuable inputs are helping me to move, thank you for that.

Please let me ask further for the WRITE transaction randomization, where I want to understand more about it to make sure I am not doing anything wrong or want to follow proper guidelines.

THIS IS MY sequence item WITH CONSTRAINTS,

class axi_seq_item_base  extends uvm_sequence_item; 
 
  rand eAxiKind kind;
  rand bit [8:0] id;
  rand bit [32:0] addr;
  rand bit [255:0] data []; 
  rand bit [4:0] length;
  rand bit [2:0] size;
  rand bit [3:0] qos;
  rand bit [5:0] user;
  rand eAxiBurstKind burst;
  rand eAxiRspKind resp;
  rand bit wait_for_rsp;
 
  constraint c_data_array { 
    data.size() == length+1; 
  }
 
  constraint c_max_length { length < 16; }
  constraint c_align { addr % 2**size == 0; }
  constraint c_burst { burst inside {axi_type_pkg::FIXED, axi_type_pkg::INCR,axi_type_pkg::WRAP};}
  constraint wrap_lenght {if (burst == axi_type_pkg::WRAP) length inside {1,3,7,15};}
 
  constraint c_dj_bytes {if (burst == axi_type_pkg::WRAP) {2**size *(length+1) == 64};}
  constraint c_dj_alow  {if (burst == axi_type_pkg::WRAP) {addr[4:0] == 0};}
  constraint c_dj_user  {if (burst == axi_type_pkg::WRAP) {addr[11:6] == user[5:0]};}
  //constraint c_dj_bit5  {if (burst == axi_type_pkg::WRAP) {addr[5] == !addr[5]};}

THIS IS MY BASE SEQUENCE, HERE I DON’T USE ANY CONSTRAINT,

class axi_base_seq extends uvm_sequence #(axi_seq_item);
  string tID;

  rand axi_type_pkg::eAxiKind s_kind;
  rand bit [8:0] s_id;
  rand bit [31:0] s_addr;
  rand bit [255:0] s_data[];
  rand bit [4:0] s_length;
  rand bit [2:0] s_size;
  rand bit [3:0] s_qos;
  rand bit [5:0] s_user;
  rand eAxiBurstKind s_burst;
  rand bit s_wait_for_rsp;

  task body();
    req = axi_seq_item::type_id::create("req");
    `uvm_info(tID,$sformatf("sequence RUNNING id=%x addr=0x%0x length=%d", s_id, s_addr, s_length),UVM_DEBUG)
    start_item(req);
    if (!req.randomize() with 
    {
      addr == s_addr;
      length == s_length;
      size == s_size;
      burst == s_burst;
      id == s_id;
      kind == s_kind;
      addr == s_addr;
      wait_for_rsp == s_wait_for_rsp;
      foreach(s_data[i]) data[i] == s_data[i];
    })
    `uvm_error(get_type_name(), "Randomize failed")
    finish_item(req);    
    `uvm_info(tID,$sformatf("sequence COMPLETE id=%x", s_id), UVM_DEBUG)    
  endtask : body

Now when I call below from my virtual sequence(please note that I have to update below code as per your guideline and use create and start methods instead of uvm_do_on_with, which I am going to do later),

        axi_base_seq        axi_wseq;
repeat (10) begin
        `uvm_do_on_with(axi_wseq, axi_seqr, 
        {
          s_kind == axi_type_pkg::WRITE;
          s_id inside {[axi_seqr.cfg_h.id_lo:axi_seqr.cfg_h.id_hi]};
          s_addr inside {['hb0000000:'hbfffffff]};
          s_length inside {[0:axi_seqr.cfg_h.max_length]};
          s_size inside {[0:axi_seqr.cfg_h.max_size]};
          s_burst == axi_type_pkg::INCR;
          s_wait_for_rsp == 1;
        })
end

For some iteration randomization works and for some iteration randomization fails and produces below error,

axi_base_seq.sv: The randomize method call failed. These constraints contribute to the set of conflicting constraints:
  constraint c_align { addr % 2**size == 0; } (axi/axi_seq_item.sv)
      addr == s_addr; (./axi/axi_base_seq.sv)
      size == s_size; (./axi/axi_base_seq.sv)
These variables contribute to the set of conflicting constraints:
state variables:
       s_addr (3033572225) [./axi/axi_base_seq.sv]
       s_size (4) [./axi/axi_base_seq.sv]
rand variables:
       addr [./axi/axi_seq_item.sv]
       size [./axi/axi_seq_item.sv]

I thought I was doing it correct , as from the virtual sequence , I gave the ranges to different control fields and then randomized it, shouldn’t it work?

Can you please explain me if the constraint need to be updated here or I need to enhance constraint in the axi_base_seq(and if that need to be matching with axi_seq_item constraints) or basically what I need to take care to avoid failing randomization?

Thank you and Best regards.