Inline constraint while using uvm_do_on_with

SystemVerilog
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4

In reply to megamind:

You can read about the sequence/sequencer flow at this UVM Cookbook page.

Instead of calling randomize(), you can just assign your fields:


  task body();
    req = axi_seq_item::type_id::create("req");
    `uvm_info(tID,$sformatf("sequence RUNNING id=%x addr=0x%0x length=%d", s_id, s_addr, s_length),UVM_DEBUG)
    start_item(req);
    req.addr == s_addr;
    req.length == s_length;
    req.size == s_size;
    req.burst == s_burst;
    req.id == s_id;
    req.kind == s_kind;
    req.addr == s_addr;
    req.wait_for_rsp == s_wait_for_rsp;
    foreach(s_data[i]) req.data[i] == s_data[i];
    finish_item(req);
    `uvm_info(tID,$sformatf("sequence COMPLETE id=%x", s_id), UVM_DEBUG)    
  endtask : body