In reply to cgales:
Thank you.
Please let me clarify the example I showed was for just explanation, WRITE transaction need to be completely random but the READ transaction should match with WRITE transaction, so READ transaction should be directed with WRITE transaction values, and for a reason it is not taking those directed values!!! which I want to know how can be best handled.
>>I would recommend not using the `uvm_do_ macros. These add a layer of complexity which make things difficult to debug. Instead, use the start_item()/randomize()/finish_item() methodology.*
I can try this, if this is the cause of the failure.
>>Additionally, if you are assigning every element of your transaction to a known value, why call randomize? I would skip calling randomize() and just assign the values required.
How can I do that here in this context? can you please show syntax for example instead of,
`uvm_do_on_with(axi_rseq, axi_seqr,
{
s_kind == axi_type_pkg::READ;
s_id == axi_wseq.req.id;
s_addr == axi_wseq.req.addr;
s_length == axi_wseq.req.length;
s_size == axi_wseq.req.size;
s_burst == axi_wseq.req.burst;
s_wait_for_rsp == axi_wseq.req.wait_for_rsp;
//##foreach(axi_wseq.req.data[k]) s_data[k] == axi_wseq.req.data[k]; //I need this for score boarding purpose, so this is my question??? please share the answer for this line.
})
What should be replaced?