Inline constraint while using uvm_do_on_with

SystemVerilog
, , , ,
6

In reply to megamind:

If you are starting a sequence from a virtual sequencer, the flow is similar:


  axi_rseq = axi_base_seq::type_id::create("axi_rseq");
  axi_rseq.s_kind == axi_type_pkg::READ;
  axi_rseq.s_id = axi_wseq.id;
  ...
  axi_rseq.start(axi_seqr);