Inline constraint while using uvm_do_on_with

In reply to cgales:

Thank you, I have updated your syntax recommendation inside my base sequence “class axi_base_seq”, as you suggested, but that did not solve the issue. Also “class my_sequence” is a virtual sequence, which I am starting in my top test, so later in the my_sequence, I am using uvm_do_on_with, as I need to pass some sequencer.

However I could solve my problem with below change in the “class my_sequence”

  `uvm_do_on_with(axi_rseq, axi_seqr, 
  {
    s_kind == axi_type_pkg::READ;
    s_id == axi_wseq.req.id;
    s_addr == axi_wseq.req.addr;
    s_length == axi_wseq.req.length;
    s_size == axi_wseq.req.size;
    s_burst == axi_wseq.req.burst;
    s_wait_for_rsp == axi_wseq.req.wait_for_rsp;
    s_data.size() == axi_wseq.req.data.size();                       //This solved the issue
    foreach(axi_wseq.req.data[k]) s_data[k] == axi_wseq.req.data[k]; //Now this line don't produce any error and randomization works well with uvm_do_on_with
  })

Do you have any further comments? Thank you.