Constraint randomization for two address regions

SystemVerilog
, , ,
1

I want to define two address regions such that they are non overlapping.

class constraint_eg;
  rand bit [1:0] enable;
  rand bit[1:0] [4:0] start_address;
  rand bit [1:0] [4:0] end_address;
 constraint adress{
    foreach(enable[ii])
        end_address[ii]>start_address[ii];
  }; 
endclass

The above code doesnot gurantee the non overlapping of the two address region defined, how can I modify my constraint so that it meets the below requirement::
end_address[ii]>start_address[ii];
and
start_address[ii+1]> end_address[ii]

2

In reply to 100rabhh:

I did it like this::

constraint valid_address{
 
    foreach(enable[ii])
    if(ii!=0)
      end_address[ii]>start_address[ii]&&(start_address[ii]>end_address[ii-1]);
    else
      (end_address[ii]>start_address[ii]);  
  };

Would be nice to get other ideas. Thanks.

3

In reply to 100rabhh:

Please use code tags making your code easier to read. I have added them for you.

See the links here: https://verificationacademy.com/forums/systemverilog/random-non-overlapping-address-memory-allocator.

4 


rand bit en[];
rand bit incr; //to randomize increasing or decreasing addr
rand bit [4:0] start_addr[];
rand bit [4:0] end_addr[];
constraint non_overlpg_addr{
    foreach(en[i]){
     (incr == 1)  ->  (end_addr[i+1] > start_addr[i+1] > end_addr[i] > start_addr[i]);
     (incr == 0)  ->  (end_addr[i] > start_addr[i] > end_addr[i+1] > start_addr[i+1]);
    }
    (en.size() == start_addr.size() == end_addr.size());
    en.size() inside {[2:5]};
    solve incr before start_addr;
    solve incr before end_addr;
}