Constraint randomization for two address regions

SystemVerilog
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2

In reply to 100rabhh:

I did it like this::

constraint valid_address{
 
    foreach(enable[ii])
    if(ii!=0)
      end_address[ii]>start_address[ii]&&(start_address[ii]>end_address[ii-1]);
    else
      (end_address[ii]>start_address[ii]);  
  };

Would be nice to get other ideas. Thanks.