I have the requirement as follow:
I have 6 regions, these regions can be of 3 types, data,buffer,control. every time a region is of control type it has to fall between the space of any of the other data regions. the buffer region has to be independent of data and control region. Although the below code is working fine but the control region always falls in between the last defined data region, for eg we have region[0] as data and region [5] as data then if region [2] is control, region[2] always falls in between region defined by region[5]. Here region[i]=end_addr[i]-startd_addr[i].
class random_generate extends uvm_sequence_item;
typedef enum{data_type,control,buffer
} rgn_type;
rand bit [7:0] start_addr;
rand bit [7:0] end_addr;
rand rgn_type rgn_kind[];
rand bit[2:0] regn_size;
`uvm_object_utils_begin(rgn_descriptor)
`uvm_field_array_enum(rgn_type,rgn_kind,UVM_ALL_ON)
`uvm_field_array_int(start_addr,UVM_ALL_ON|UVM_HEX)
`uvm_field_array_int(end_addr,UVM_ALL_ON|UVM_HEX)
`uvm_field_array_int(regn_size,UVM_ALL_ON|UVM_HEX)
`uvm_object_utils_end
function new(string name = "RgnDescriptor");
super.new(name);
rgn_kind = new[6];
start_addr = new[6];
end_addr = new[6];
endfunction: new
constraint SOLVER{
solve rgn_kind before start_addr;
solve rgn_kind before end_addr;
}
constraint OVERLAP {
foreach (start_addr[i]) {
start_addr[i][7]==0;
foreach (start_addr[j]) {
if ((rgn_kind[i]==data_type) && (i!=j)&&(rgn_kind[j]==control)) {
( start_addr_in_64KB[j] inside {[start_addr[i]:end_addr[i]]} );
( end_addr_in_64KB[j] inside {[start_addr[i]:end_addr[i]]} );
}
}
}
foreach (start_addr[i]) {
if (regn_size[i]>0) {
end_addr[i] == ((start_addr[i] + regn_size[i])-1);
} else {
end_addr[i] == (start_addr[i]);
}
}
}
endclass
module abc();
random_generate rgen=new("region");
repeat(5) begin
if (!rgen.randomize() with {
}
) `uvm_fatal("RANDOMIZATION FAILED", "rgen.randomize()")
end
endmodule