Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • UVMF - One Bite at a Time
      • Introduction to UVM
      • Basic UVM
      • UVM Debug
      • Advanced UVM
      • UVM Connect

    • Featured Courses

      • Portable Stimulus Basics
      • Introduction to DO-254
      • SystemVerilog OOP for UVM Verification
      • Power Aware Verification
      • Power Aware CDC Verification
      • Assertion-Based Verification
      • Metrics in SoC Verification

    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal Coverage
      • Formal-Based Technology: Automatic Formal Solutions
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizon - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Automated or Direct Formal Analysis - Fremont | 10/15
      • DVClub - Boston | 10/18
      • Mentor Forum - Helsinki | 10/29
      • DVCon Europe - Munich | 10/29 - 10/30
      • AMS / Functional Verification Tech Day - Herzliya | 11/6
      • Events Calendar

    • On Demand Seminars

      • UVM 1800.2 & Updated UVM Cookbook
      • Debug
      • FPGA Verification
      • All On-Demand Seminars

    • Recording Archive

      • DAC 2019 Session Recordings
      • User2User Silicon Valley 2019
      • Portable Stimulus from IP to SoC
      • Wilson Research Group - 2018 Results
      • All Recordings

    • Mentor Training Center

      • SystemVerilog for Verification
      • SystemVerilog UVM
      • SystemVerilog UVM Advanced
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Advanced OOP
      • UVM Transactions and Sequences
      • UVM Monitors and Agents
      • Functional Verification Library
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - June 2019
      • Verification Horizons - February 2019
      • Verification Horizons - November 2018
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • SystemVerilog
      • Functional Verification Library
Ask a Question
SystemVerilog
  • Home /
  • Forums /
  • SystemVerilog /
  • Range must be bounded by constant expressions

Range must be bounded by constant expressions

SystemVerilog 3879
ssingh
ssingh
Forum Access
38 posts
February 01, 2013 at 5:21 am

I am trying to implement the following in systemverilog.

always_comb
    begin
	for(int i=0;i<=124;i=i+6)
	    begin
	        offset = DFF_data[ ((2*i)+1):(2*i) ]; // Error !	
		data_output[i+offset]= data_input[i];
	    end
   end

I get the following error in the line marked above: Range must be bounded by constant expressions. I can see the error ocuurs beacuse of the use of "i" in defining the range of array DFF_data. But writing this without "i" seems impractical. I am using QuestaSim 10.1d. Has anyone come across such a situation?

Replies

Log In to Reply

Solution

Solution

dave_59
dave_59
Forum Moderator
7025 posts
February 01, 2013 at 7:41 am

Verilog integral expressions must have a constant width determined at compile time.

Use need to use a indexed part-select which allows you to specify a variable base expression with a constant width. (this comes from Verilog)

logic [15:0] down_vect;
logic [0:15] up_vect;
down_vect[lsb_base_expr +: width_expr]
up_vect[msb_base_expr +: width_expr]
down_vect[msb_base_expr -: width_expr]
up_vect[lsb_base_expr -: width_expr]

So you can write

offset = DFF_data[ (2*i) +: 1 ];

ssingh
ssingh
Forum Access
38 posts
February 05, 2013 at 4:27 am

In reply to dave_59:

Thank you

vishalkewlani
vishalkewlani
Full Access
6 posts
February 10, 2015 at 11:23 pm

In reply to ssingh:

Thank you very much

raja.kuraku
raja.kuraku
Full Access
16 posts
June 01, 2015 at 5:32 am

In reply to vishalkewlani:

Hello Guys,

I am facing the same problem with 2variables.

offset = DFF_data[ ((2*j)+7):(2*i) ];

Here i am having the 2 variables i&j.
So how to do part select.
Means to say that my width will vary.

Please answer the question.

dave_59
dave_59
Forum Moderator
7025 posts
June 01, 2015 at 8:33 am

In reply to raja.kuraku:

You can use a shift and mask operation

offset = (DFF_data >> 2*i) & 2**(width)-1

I'll leave it to you or someone else to figure out the width expression and make sure I have the right operator precedence.

saroj kumar sahoo
saroj kumar sahoo
Full Access
2 posts
January 09, 2018 at 10:21 pm

In reply to dave_59:

module wr_strb;
bit [15:0] Data = 'hFFFF;
bit [15:0] WDATA;
 
task strobe(int r);
WDATA[(4*r-1):0] = 'hx;
WDATA[15:(4*r)] =  Data[15:(4*r)];
$display("WDATA = %0h",WDATA);
endtask
 
initial
begin
strobe(2);
end
endmodule

********************************************************************************
Hi Dave,
i'm getting an error : "Range must be bounded by constant expression" for the above code.
If you have any solution for this please guide me.

thanks and regards,
Saroj Kumar Sahoo

dave_59
dave_59
Forum Moderator
7025 posts
January 10, 2018 at 10:46 am

In reply to saroj kumar sahoo:

function void strobe(int r);
  bit [15:0] mask;
  mask = (15'b1 << 4*r) - 1;
  WDATA =  Data ^ (mask & 15'hXXXX);
  $display("WDATA = %0h",WDATA);
endfunction
saroj kumar sahoo
saroj kumar sahoo
Full Access
2 posts
January 11, 2018 at 5:15 am

In reply to dave_59:

Thank you very much Dave.

mansi m joshi
mansi m joshi
Forum Access
5 posts
August 08, 2018 at 10:30 pm

data_in[7*(j+1)+j:8*j] // while i am doing this in sv this error comes----> Range must be bounded by constant expressions how to get the same functionality

dave_59
dave_59
Forum Moderator
7025 posts
August 09, 2018 at 12:03 am

In reply to mansi m joshi:
data_in[j+:8]

mansi m joshi
mansi m joshi
Forum Access
5 posts
August 09, 2018 at 12:21 am

hello dave in this above example if only 8 bit slicing needs for ex : [7:0] [15:8] [23:16] [31:24] [39:32] [47:40] [55:48] [63:56] and so on

mansi m joshi
mansi m joshi
Forum Access
5 posts
August 09, 2018 at 1:46 am

its done by using this : data_in[8*(j):8]

© Mentor, a Siemens Business, All rights reserved www.mentor.com

Footer Menu

  • Sitemap
  • Terms & Conditions
  • Verification Horizons Blog
  • LinkedIn Group
SiteLock