How to write structural Logic in Class

SystemVerilog
, , , , ,
1 
module faa(input a, b, cin, output s, cout);
  wire w1,w2,w3;
  ha x1(.a(a),.b(b),.s(w1),.c(w2));
  ha x2(.a(w1),.b(cin),.s(s),.c(w3));
  or1 x3(.a(w2),.b(w3),.y(cout));
endmodule


`include "fa_driver.sv"
`include "or1.sv"
`include "ha.sv"
class fa_sb;
  bit ha;
  bit or1;
  bit s_exp;
  bit cout_exp;
  
  task input_data(fa_trans trans_in);
    ha x1(.trans_in.a(trans_in.a),.trans_in.b(trans_in.b),.trans_in.s(w1),.trans_in.c(w2));
   ha x2(.trans_in.a(w1),.trans_in.b(trans_in.cin),.trans_in.s(s_exp),.trans_in.c(w3));
 or1 x3(.trans_in.a(w2),.trans_in.b(w3),.trans_in.y(cout_exp)); 
    endtask
  
  task output_data(fa_trans trans_out);
    if(trans_out.s==s_exp && trans_out.cout==cout_exp)
      $display("PASS");
    else
      $display("FAIL");
    endtask
    
  endclass
`endif

** Error: C:/questasim_10.0b/Nano SV Projects/fa_sb.sv(13): near “x1”: syntax error, unexpected IDENTIFIER

2

In reply to Soobaan:

You cannot instantiate structural logic in procedural code. What you can is use variables from procedural code as inputs to structural code.

3

In reply to dave_59:

In reply to Soobaan:
You cannot instantiate structural logic in procedural code. What you can is use variables from procedural code as inputs to structural code.

HI Dave,
can you show an example how to connect procedural to structural.
Actually this is a small example, I thought to solve this first as I am working on a big project in which I have almost 70 outputs logic… which I don’t have much time to implement Data flow type logic for this many outputs for Scoreboard/ checker.