Local vs protected in SV class

SystemVerilog
,
1

I would like to confirm my understanding of local and protected in a SV class.

local variable - this is local to the class where it is specified. Neither it is available in the derived class or module that instantiates this class

protected variable - this is not available in the module that instantiates but is available to the derived class

I assume my understanding is correct.

Another question, is it possible to change the access type of a variable in the derived class, that is defined in the base class.
To elaborate, x variable is declared as protected in base class. Can it be changed to local in derived class closing its access for the subsequent derived classes?

2

In reply to verif_learner:

Yes, excecpt that the rules applies to anywhere outside the class, not just other modules that instantiate this class.

No, you cannot change the access type.

4

In reply to yusuf_eren:
Actually what you showed is not recommended basically you created a new variable with the exact same name in the child1 class you can see this if you print the object, what dave described still valid.

# KERNEL: test1 = '{[child1]:'{[base_class]:'{public_flag:0}, public_flag:0}}
# KERNEL: test2 = '{[base_class]:'{public_flag:0}}

HTH,

-R

6
1. Local -> Only that class, we can't access child/outside the class 

class A;
local int local_variable;
endclass : A
module top;
A a=new;
a.local_variable = 10;
endmodule : top

Output Error : Illegal class variable access

2.a Protected → With in family only (Base and derived class)
Let’s try to access via module


class A;
protected int protected_variable;
endclass : A
module top;
A a=new;
a.protected_variable = 10;
endmodule : top

Output Error : Illegal class variable access

2.b.Using derived class is possible


class A;
    protected int protected_variable;
endclass : A
class B extends A;
function void display(); 
    protected_variable++;
endfunction
endclass

Possible