How to use packages in class

SystemVerilog
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1

I saw in the thread below that packages cannot be directly imported into classes:
https://verificationacademy.com/forums/systemverilog/why-it-illegal-import-package-contents-class-scope

But I didn’t understand what is the solution. If I have a package with an enum inside and I want to reference that enum in a class, how can I achieve this? Do I import outside of the class instead? If so, what is the ‘scope’ of that import?

class some_class extends some_other_class;
   //import my_pkg::*; // not allowed
   struct {
      enum_from_my_pkg_e my_enum;
      // other stuff
   } my_struct;

   // other class stuff
endclass
2

In reply to atashinchi:
The solution is importing the package in the same scope where you are defining the class. That is usually in another package.

3

Thanks Dave. In a somewhat related note: I have a .svh file with interfaces. I will

`include

this file in some other .sv file (since I cannot put interfaces in packages). If an interface itself references an enum from another package, do I import the package inside the interface or outside?

interface my_intf_i;
   import some_pkg::*; // is this allowed?
   some_enum_from_pkg_e my_enum;
   // other interface stuff
   // modport stuff
endinterface
4

In reply to atashinchi:

You can import a package anywhere you can declare a variable (except within a class scope).

The best place to put an import statement is inside a module/interface/package. If your module/interface ports need identifiers from a package, you can put the import statement as part of its header declaration.

Putting import statements outside a module/interface/package (which means it is in the $unit scope) is a bad idea for larger projects–it pollutes the namespace.