Section 26.3 of the SystemVerilog-2012 LRM contains the statement that “It shall be illegal to have an import statement directly within a class scope.” and does not give any rationale that I can see. This does not inconvenience me since I use explicit references to package contents, but have often wondered why this is prohibited.
In reply to sbellock:
This restriction is similar to the using namespace restriction in C++. There are some problems with the rules for searching for symbols in a package versus searching the class inheritance hierarchy. I also think there would be some expectation that importing a symbol into a class would make the symbol available in the extended class, and it could not work that way.