System Verilog coverge sampling using class instead of Mod

SystemVerilog
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1

Hi,

I am trying to sample the cover groups inside the class instead of module while I am creating new to the cover group I am getting an error. Can anyone Please help me which type of function or task I can use to sample the cover group inside the class.

Thanks in Advance,
Harshavardhan.

2

In reply to Harsha vardhan:

Change your code.

Impossible to fix your error as you have not said what it is.

3

In reply to dave_59:
Please find the code: