Base class handle for extended class is not working in SystemVerilog

SystemVerilog
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1

Hi All,

I am writing following program in System Verilog

class base;
  int a = 5;
endclass

class extend extends base;
  int b = 1;
endclass

module test;

  initial begin
    base m_base;
    extend m_extend;
    
    m_base = new();
    m_extend = new();
    m_base = m_extend;
    $display(m_base.b);
  end
endmodule

It gives me Error,
Error-[MFNF] Member not found
testbench.sv, 18
“m_base.”
Could not find member ‘b’ in class ‘base’, at “testbench.sv”, 1.

I am not able to understand why it is giving such error

2

In reply to milinraijada:

It is because m_base is of type base, which doesn’t have ‘b’ as a member. Class base only has ‘a’ as a member. When you assign the handle of class extend to a class base, you will only be able to access the members of class base.

3

In reply to milinraijada:
You should take a look at my short course on SystemVerilog OOP, especially the second session on inheritance and class variables.