Best Practice for Unit Tests Extending Chip-Level Tests

UVM
,
1

Hello,

I have a chip-level test with the structure of a base_test and all specific test cases extend from base_test. The environment consists of an I2C UVC and a register model with backdoor access. I want to create a unit test environment for a sub-component of the chip-level that would use the same register model and I2C UVC. The HDL path for backdoor access will differ for the unit test and some of the base_test functionality is not possible for the unit test.

My question is this: Is it okay practice to use `ifdef macros to reuse the chip-level verification components (i.e. using a different hdl path, not compiling code only applicable to the chip-level)? Ideally I’d like to be able to run the same tests for both chip-level and unit level and this seems to be the most feasible way to do so.

Not sure what code I can share, but if there’s more context I can provide let me know.

2

It’s difficult to answer this question in a generic way. I know that the RAL model can be set up hierarchically to build the address maps without needed `ifdefs , but that may not always match how your design accesses the registers.

Also consider how code and functional coverage might be affected it you want to merge unit with chip level testing.