How can I use parent class's member variable in systemverilog?

SystemVerilog
,
1

Dear All,

I’m trying to understand an overriding class member in systemverilog with the below example code, As I understand, If I want to override then do use “extend” such as class child_class extends parent_class. if then, I can override the parent’s variables.

 class parent_class;
  bit [31:0] addr;
  
  function display();
    $display("Addr = %0d",addr);
  endfunction
endclass

 class child_class extends parent_class;
  bit [31:0] data;
  
  function display();
    $display("Data = %0d",data);
  endfunction
endclass

module inheritence;
  initial begin
    parent_class d=new();
    child_class c=new();
    c.addr = 10;
    c.data = 20;
    d.addr = 30;
    c.addr = 10;
    
    c.display();
    d.display();
  end
endmodule

and I’ve got the below result,
Data = 20
Addr = 30

but I thought that it supposed to be
Data = 20
Addr = 10 not 30.

How can I use parent’s member ?
Is there any way to implement overriding without super?

2

In reply to sylee:

I recommend against using the terms parent and child when referring to OOP inheritance. Parents create(construct) children and they are distinct objects from their parents. When you inherit property, that property becomes yours and all your property is part of one object.

You constructed two distinct objects that both share a common base class type. So
c.addr and
d.addr are two separate variables. However, your extended class “child_class” has direct access to
addr defined in its base class. So you could have written the extended class function as

 function display();
    $display("Addr = %0d",addr);
    $display("Data = %0d",data);
  endfunction

But it’s better to call super.display(). That way if you change the base class, you only need to modify the base class and not all of its extensions.

I highly recommend watching my course on SystemVerilog OOP.

3

In reply to dave_59:

In reply to sylee:
I recommend against using the terms parent and child when referring to OOP inheritance. Parents create(construct) children and they are distinct objects from their parents. When you inherit property, that property becomes yours and all your property is part of one object.
You constructed two distinct objects that both share a common base class type. So
c.addr and
d.addr are two separate variables. However, your extended class “child_class” has direct access to
addr defined in its base class. So you could have written the extended class function as

 function display();
$display("Addr = %0d",addr);
$display("Data = %0d",data);
endfunction

But it’s better to call super.display(). That way if you change the base class, you only need to modify the base class and not all of its extensions.
I highly recommend watching my course on SystemVerilog OOP.

Thanks, that’s what I want to know that between super and another way.