How can I use parent class's member variable in systemverilog?

SystemVerilog
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2

In reply to sylee:

I recommend against using the terms parent and child when referring to OOP inheritance. Parents create(construct) children and they are distinct objects from their parents. When you inherit property, that property becomes yours and all your property is part of one object.

You constructed two distinct objects that both share a common base class type. So
c.addr and
d.addr are two separate variables. However, your extended class “child_class” has direct access to
addr defined in its base class. So you could have written the extended class function as

 function display();
    $display("Addr = %0d",addr);
    $display("Data = %0d",data);
  endfunction

But it’s better to call super.display(). That way if you change the base class, you only need to modify the base class and not all of its extensions.

I highly recommend watching my course on SystemVerilog OOP.