OOPS terminologies in SV

SystemVerilog
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1

I would like to get the terms used in SV world with respect to OOPS correctly.

Let us assume the following,

  1. A derives from B
  2. C derives from A
  3. D instantiates C

is B called parent of A?
is B super parent of C?
what is D called with respect to C?

2

In reply to verif_learner:
I recommend against using parent and child when referring to OOP inheritance. Parents create(construct) children and they are distinct objects from their parents. When you inherit property, that property becomes yours and all your property belongs to one object. Use base and extended.

The UVM uses terms parent and child to refer to relationships between objects when build a hierarchical tree/graph structure. The class uvm_component has a handle to its parent and handles to all its children so that you can traverse the hierarchical structure. This terminology is used in most programming languages and is independent of OOP.

3

In reply to dave_59:

Ok, got it. Base and derived/extended class for inheritance.
Parent and child for instantiation.

Thanks,