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May 2026

Join Me at DVClub Austin - May 20, 2026
Simulation May 11, 2026 Harry Foster link

April 2026

Why DFT Verification Signoff Is the Hidden Risk Threatening Your Next Tapeout
Design For Test Apr 14, 2026 Jake Wiltgen link
PCI Express 8.0: Powering AI, Cloud, and HPC with Transformative Interconnect Technology
Verification IP Apr 09, 2026 Gyanaranjan Khuntia - Siemens Eda link

March 2026

DVCon US Keynote: Why Verification Must Evolve in the Convergence Era
Machine Learning Mar 25, 2026 Harry Foster link

February 2026

Siemens at DVCon U.S. 2026
Planning, Measurement and Analysis Feb 22, 2026 Dennis Brophy link
Beyond Simulation: Unlocking Absolute Certainty in Hardware Design with Formal Verification
Formal Verification Feb 16, 2026 Nicolae Tusinschi link

January 2026

System Verifier
Machine Learning Jan 05, 2026 Julie Weber link

December 2025

FutureCast 2026: A Special Holiday Edition of BUGGED OUT
Planning, Measurement and Analysis Dec 09, 2025 Harry Foster link

VA Live - Hudson, MA

Tuesday, June 9, 2026 | 9:00 AM - 5:00 PM EDT

This seminar empowers design engineers and verification teams with knowledge and tools for advanced AI automation and intelligent verification.

BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

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Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

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