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  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages
    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage
    • Techniques & Tools

      • Verification IQ
      • Verification IP
      • Static-Based Techniques
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
      • Advanced UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
    • UVM Forum

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      • UVM Forum
    • SystemVerilog Forum

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      • SystemVerilog Forum
    • Coverage Forum

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      • Coverage Forum
    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns
    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns
    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines
    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Featured & On-Demand

      • RISC-V Design - Webinar
      • Exploring Formal Coverage
      • Processor Customization
      • Interconnect Formal
      • Formal and the Next Normal
      • Formal Verification Made Easy
      • Data Independence and Non-Determinism
      • Exhaustive Scoreboarding
      • Visualizer Debug Environment
      • Webinar Calendar
    • On-Demand Library

      • SystemVerilog Assertions
      • Practical Flows for Continuous Integration
      • Continuous Integration
      • Questa Verification IQ
      • Avery & Siemens VIP
      • Protocol and Memory Interface Verification
      • HPC Protocols & Memories
      • Preparing for PCIe 6.0: Parts I & II
      • High Defect Coverage
      • SoC Design & Functional Safety Flow
      • Complex Safety Architectures
      • All On-Demand Recordings
    • Recording Archive

      • Lint vs Formal AutoCheck
      • FPGA Design Challenges
      • Design Solutions as a Sleep Aid
      • Fix FPGA Failures Faster
      • CDC and RDC Assist
      • The Dog ate my RTL
      • Questa Lint & CDC
      • Hierarchical CDC+RDC
      • Improving Initial RTL Quality
      • CDC Philosophy
      • Hardware Emulation Productivity
      • The Three Pillars of Intent-Focused Insight
      • All Webinar Topics
    • Conferences & WRG

      • 2022 Functional Verification Study
      • Improving Your SystemVerilog & UVM Skills
      • Automotive Functional Safety Forum
      • Aerospace & Defense Tech Day
      • Siemens EDA Functional Verification
      • Industry Data & Surveys
      • DVCon 2023
      • DVCon 2022
      • DVCon 2021
      • Osmosis 2022
      • All Conferences
    • Siemens EDA Learning Center

      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

      • Verification IQ
      • Verification Horizons Blog
      • Technical Resources
    • Verification Horizons Publication

      • Verification Horizons - July 2023
      • Verification Horizons - March 2023
      • Verification Horizons - December 2022
      • Issue Archive
    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Academy News
      • Contact Us
    • Training

      • Learning @OneGlance (PDF)
      • SystemVerilog & UVM Classes
      • Siemens EDA Classes
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16759 questions in All Topics

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    SOLVED
    REPLIES
    VIEWS
    POSTED
    UPDATED
  • Fatal: (SIGSEGV) Bad handle or reference. # Time: 0 ns Iteration: 48 Process: /uvm_pkg::uvm_task_phase::execute/#FORK#137(#ublk#215181159#137)_4f62366f File
    3  
    57  
    19 hours 37 min ago
    by zid  
    17 min 36 sec ago
    by dave_59  
  • How to sample a UVM monitor if clock is not there
     
    6  
    21 min 41 sec ago
    by kulua  
    21 min 41 sec ago
    No activity yet  
  • SPI frame format
     
    8  
    3 hours 50 min ago
    by m_v  
    3 hours 50 min ago
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  • Binding Interface to internal DUT
    1  
    72  
    1 day 1 hour ago
    by Hassan Khaled  
    16 hours 28 min ago
    by dave_59  
  • my randomization is failing
    11  
    278  
    2 weeks 5 days ago
    by Ashishkumar072  
    10 hours 34 min ago
    by ashish_saroj  
  • How to access a changing RTL path ?
    9  
    81  
    1 day 3 hours ago
    by Mark_128  
    15 hours 27 min ago
    by dave_59  
  • Difference in output using ##[0:$] $rose( b ) V/S $rose( b )[->1]
    5  
    353  
    1 week 2 days ago
    by Have_A_Doubt  
    1 week 2 days ago
    by ben@SystemVerilog.us  
  • Port directions in Modports
    3  
    76  
    1 week 4 days ago
    by acpatel5  
    1 day 22 hours ago
    by dave_59  
  • connecting the dut signals with interafce signals in the test bench top
    3  
    61  
    6 days 10 hours ago
    by lohithkumar.shivamurthy@tessolve.com  
    1 day 22 hours ago
    by dave_59  
  • Illegal range in part select
    1  
    85  
    3 days 2 hours ago
    by Abuzar Gaffari  
    1 day 22 hours ago
    by dave_59  
  • How to get array of coverpoints
    15  
    21,745  
    9 years 11 months ago
    by prasads  
    1 day 22 hours ago
    by boss8032  
  • Dynamic cast - Classes
    2  
    76  
    1 week 3 days ago
    by acpatel5  
    1 day 23 hours ago
    by acpatel5  
  • Using goto repetition
    2  
    93  
    2 days 18 hours ago
    by MICRO_91  
    2 days 3 hours ago
    by MICRO_91  
  • why we take separate bus for WDATA and RDATA in APB protocol
     
    66  
    1 week 2 days ago
    by satyajeett  
    1 week 2 days ago
    No activity yet  
  • why we have steup phase in apb
     
    33  
    6 days 9 hours ago
    by satyajeett  
    6 days 9 hours ago
    No activity yet  
  • can we use set_report_severity_id_override twice in testcase
    2  
    49  
    2 days 22 hours ago
    by shawnbay  
    2 days 15 hours ago
    by shawnbay  
  • SVA to check next 'read' request
    4  
    338  
    1 week 2 days ago
    by MICRO_91  
    2 days 17 hours ago
    by MICRO_91  
  • Is there a way to use/execute the printf based debug information from the C Test in CPU
    6  
    83  
    6 days 17 hours ago
    by desperadorocks  
    2 days 19 hours ago
    by desperadorocks  
  • difference between break and disable (disable within a loop)
    1  
    49  
    3 days 5 hours ago
    by Madhan S  
    2 days 19 hours ago
    by dave_59  
  • Declaring an array to store real values
    2  
    76  
    3 days 6 hours ago
    by skyhome0911  
    2 days 19 hours ago
    by dave_59  

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16,858 Questions

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90,127 Users

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