Topics tagged ral

Topic	Replies	Views	Activity
RAL set() method followed by update() method modify all 32 bits of a 32 bit register! UVM UVM , RAL	1	28	June 18, 2025
Encoding/Decoding with RAL UVM RAL	4	39	May 14, 2025
Using callbacks to change access to control fields within the same register UVM UVM , RAL , UVM-callback	1	39	May 12, 2025
How to close the print info,just like "[RegModel] Read register via user backdoor...",when i set "+UVM_VERBOSITY=UVM_HIGH"? UVM RAL	4	40	April 22, 2025
Modeling behavior of a register that is dependant on another register UVM RAL	3	49	March 28, 2025
UVM RAL model for register and memory with overlapping address and accessing them using the same interface UVM RAL , RAL-register-UVM , uvm-ral	4	113	March 27, 2025
I cannot find any implementations of a class that extends uvm_reg_file UVM SystemVerilog , UVM , RAL , System-Verilog , uvm-ral , uvm_ral , uvm_reg_file , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , register-file , register-model-structure	1	48	March 23, 2025
UVM RAL: Mapping Same Register Block to Two Address Ranges UVM RAL , uvm-ral	0	38	March 12, 2025
Modelling the register fields via callbacks UVM RAL	0	25	March 7, 2025
Coverage for volatile registers in UVM RAL UVM UVM , Coverage , RAL , uvm-ral	3	86	March 6, 2025
UVM RAL writes, reads and prediction UVM UVM , RAL	0	61	February 11, 2025
Implementing Outstanding AXI transactions using RAL UVM UVM , RAL , uvm-ral	1	158	December 19, 2024
RAL Coverage , Multiple Instance issue UVM RAL	2	80	November 26, 2024
Factory in RAL , create vs new UVM RAL	1	75	November 19, 2024
Mirrored value in frontdoor and backdoor UVM RAL	1	89	November 19, 2024
I want to apply RAL for UART Interface that has TX signal only UVM RAL	1	60	November 11, 2024
Register abstraction layer , where can i define the offset of the registers? UVM RAL	1	57	November 4, 2024
Requirement of both local_map & map UVM RAL , uvm-register-model	2	73	October 30, 2024
Advantage of calling set() over write() UVM UVM , RAL , uvm-ral	1	270	October 20, 2024
RESET Assertion with out clock dependency SystemVerilog OVM , SystemVerilog , Announcements , UVM , assertion , RAL , SVA , system-verilog-assertion-SVA , Assertion-Based-Verification , constraint-randomization , assert-property , Assertion-system-verilog	1	147	October 18, 2024
Handling multiple RAL request simultaneously UVM UVM , RAL	2	152	September 26, 2024
Can't explain different behavior of 2 RAL registers with W1C fields UVM RAL	1	103	September 20, 2024
How to Selectively skip STS ( RO ) registers in bit_bash UVM UVM , RAL , uvm_reg_bit_bash	0	93	September 19, 2024
How to check the register is implemented in UVM RAL with the address UVM UVM , RAL , uvm_reg	1	173	September 3, 2024
Testing of Read/Write register through RAL when bug is there UVM UVM , RAL	1	154	August 22, 2024
How to get Backdoor Access for Memory? UVM RAL	0	150	August 8, 2024
Proper reg_map has not picked up UVM RAL	5	159	July 4, 2024
UVM register model UVM RAL , uvm-ral	0	148	July 1, 2024
RAL Register access UVM RAL	3	337	May 16, 2024
Skipping a register field from comparison with RAL UVM RAL , uvm_ral , RAL-UVM	10	646	May 15, 2024

RAL set() method followed by update() method modify all 32 bits of a 32 bit register!

UVM

UVM , RAL

1

28

June 18, 2025

Encoding/Decoding with RAL

UVM

RAL

4

39

May 14, 2025

Using callbacks to change access to control fields within the same register

UVM

UVM , RAL , UVM-callback

1

39

May 12, 2025

How to close the print info,just like "[RegModel] Read register via user backdoor...",when i set "+UVM_VERBOSITY=UVM_HIGH"?

UVM

RAL

4

40

April 22, 2025

Modeling behavior of a register that is dependant on another register

UVM

RAL

3

49

March 28, 2025

UVM RAL model for register and memory with overlapping address and accessing them using the same interface

UVM

RAL , RAL-register-UVM , uvm-ral

4

113

March 27, 2025

I cannot find any implementations of a class that extends uvm_reg_file

UVM

SystemVerilog , UVM , RAL , System-Verilog , uvm-ral , uvm_ral , uvm_reg_file , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , register-file , register-model-structure

1

48

March 23, 2025

UVM RAL: Mapping Same Register Block to Two Address Ranges

UVM

RAL , uvm-ral

0

38

March 12, 2025

Modelling the register fields via callbacks

UVM

RAL

0

25

March 7, 2025

Coverage for volatile registers in UVM RAL

UVM

UVM , Coverage , RAL , uvm-ral

3

86

March 6, 2025

UVM RAL writes, reads and prediction

UVM

UVM , RAL

0

61

February 11, 2025

Implementing Outstanding AXI transactions using RAL

UVM

UVM , RAL , uvm-ral

1

158

December 19, 2024

RAL Coverage , Multiple Instance issue

UVM

RAL

2

80

November 26, 2024

Factory in RAL , create vs new

UVM

RAL

1

75

November 19, 2024

Mirrored value in frontdoor and backdoor

UVM

RAL

1

89

November 19, 2024

I want to apply RAL for UART Interface that has TX signal only

UVM

RAL

1

60

November 11, 2024

Register abstraction layer , where can i define the offset of the registers?

UVM

RAL

1

57

November 4, 2024

Requirement of both local_map & map

UVM

RAL , uvm-register-model

2

73

October 30, 2024

Advantage of calling set() over write()

UVM

UVM , RAL , uvm-ral

1

270

October 20, 2024

RESET Assertion with out clock dependency

SystemVerilog

OVM , SystemVerilog , Announcements , UVM , assertion , RAL , SVA , system-verilog-assertion-SVA , Assertion-Based-Verification , constraint-randomization , assert-property , Assertion-system-verilog