Upcoming RDC Assist Webinar

Questa RDC Assist – Improving designer productivity and enabling faster RDC verification closure with machine learning

Wednesday, May 22nd | 8:00 AM US/Pacific

Learn more and register.

  1. Session Slides

    Session Title



    Smart Verification, Faster is not enough!

    - Harry Foster | Chief Scientist Verification
    Welcome to the dawn of EDA 4.0, a groundbreaking era marked by a profound revolution in electronic design automation, all propelled by the incredible capabilities of artificial intelligence. In this presentation, we'll embark on a captivating journey through the technological ages, beginning with the era of electrification and culminating in the era of cognification. Alongside this narrative, we'll trace the parallel evolution of electronic design automation, spanning from its inception in EDA 1.0 to its current pinnacle, EDA 4.0. Throughout this voyage, we will provide a compelling, data-driven case for why this evolution is not merely a luxury but an absolute necessity in our rapidly changing world. Brace yourselves, for EDA 4.0, driven by the immense potential of artificial intelligence and machine learning, is poised to revolutionize every facet of electronic design. PDF
    Verify designs created in MATLAB or Simulink within subsystem or full-chip UVM simulations

    - Bob Oden | UVM Field Specialist
    ASIC’s and FPGA’s increasingly include DSP, algorithm, AI, and ML blocks created using MATLAB or Simulink. Simulating these blocks within the context of adjacent RTL is required for verifying integration and system performance. Cooperation between Mathworks and Siemens has produced an automated flow for verifying these blocks within subsystem and full chip UVM based simulation environments. In this presentation and demonstration you will learn how to automatically generate a UVM environment that is reusable from block to chip as well as from simulation to emulation. PDF
    When it Comes to Artificial Intelligence and Machine Learning, Siemens Has You Covered

    - Tom Fitzpatrick | Strategic Verification Architect
    Don’t Worry about Skynet or HAL 9000. At Siemens, we’ve always viewed our role as helping you be better at verifying the functionality of your designs. We’ve invested huge amounts of time and talent over the years to add the latest technologies to every aspect of functional verification, and with the current revolution in Artificial Intelligence and Machine Learning (AI/ML), we’re not about to stop now. You may have been told many different things about what AI/ML can do in the area of functional verification, but this presentation will give you the real story. Beginning with an overview of what AI/ML actually means and what technology is actually available today, we’ll explore many of the ways that we’re incorporating this exciting technology across our product portfolio. One key area where we’re seeing great results is in Verification Management, where our Verification IQ platform incorporates key elements of AI/ML in a data-driven verification approach to coverage and product lifecycle management. But as important as AI/ML is to the future of verification, it’s not the only area where we’re investing. We’ll also cover other major investments we’re making across our Questa family of verification tools, from Simulation to Design Solutions and beyond, all with the aim of making it easier for you to ensure that your designs will work correctly on the first pass. PDF
    Success with Continuous Integration and Continuous Development (CI/CD) Pipeline using automated checking

    - Afzal Usmani | Manager Advanced Verification
    Mistakes happen, but finding and fixing issues late in programs increases overall program scope, as well as schedule and resource requirements. Competitive pressures push teams constantly to do more. Functional verification teams face significant challenges to build testbenches quickly, uncover design issues and enable rapid debug. Incomplete or incorrect bug fixes (or even a hurried introduction of new bugs) compound the problem. Utilizing CI flows with static and sequential formal solutions enable early detection and quick debug of these RTL issues. PDF
    Industry Trends in Functional Verification!

    - Harry Foster | Chief Scientist Verification
    This talk unveils the outcomes of a comprehensive two-decade-long double-blind industry study focusing on the functional verification of Application-Specific Integrated Circuit (ASIC) and Field-Programmable Gate Array (FPGA) designs, with a focus on the aerospace and defense markets. The insights derived from this extensive research endeavor shed light on a myriad of pressing challenges, notably the growing prevalence of bug escapes into production and the persistent issue of missed project schedules. Finally, this talk offer valuable insights and strategies for mitigating these trends, providing a roadmap towards enhanced verification practices and more reliable product development processes. PDF