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  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
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      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IQ
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      • Static-Based Techniques
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      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
      • Advanced UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

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      • Coverage Forum

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Featured & On-Demand

      • UCIe Verification IP
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      • Formal Verification Made Easy
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      • Exhaustive Scoreboarding
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      • Webinar Calendar

    • On-Demand Library

      • SystemVerilog Assertions
      • Practical Flows for Continuous Integration
      • Continuous Integration
      • Questa Verification IQ
      • Avery & Siemens VIP
      • Protocol and Memory Interface Verification
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      • Preparing for PCIe 6.0: Parts I & II
      • High Defect Coverage
      • SoC Design & Functional Safety Flow
      • Complex Safety Architectures
      • All On-Demand Recordings

    • Recording Archive

      • Lint vs Formal AutoCheck
      • FPGA Design Challenges
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      • Fix FPGA Failures Faster
      • CDC and RDC Assist
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      • Questa Lint & CDC
      • Hierarchical CDC+RDC
      • Improving Initial RTL Quality
      • CDC Philosophy
      • Hardware Emulation Productivity
      • The Three Pillars of Intent-Focused Insight
      • All Webinar Topics

    • Conferences & WRG

      • 2022 Functional Verification Study
      • Improving Your SystemVerilog & UVM Skills
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      • Industry Data & Surveys
      • DVCon 2023
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    • Siemens EDA Learning Center

      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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  • Debug

Debug

Debug

Debug takes a significant proportion of any design or verification engineer’s time. An Intuitive and powerful HW and SW debug solution is needed to improve debug productivity across ESL, formal, RTL/gate-level simulation and emulation platforms. In addition to being intuitive and easy to use, a debug methodology needs several powerful attributes that improve debug productivity for SystemVerilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.

Below please find the UVM Debug course, on-demand webinars covering tracing, adding signals and more plus sessions on the Visualizer Debug Environment to get you started.

Visualizer On-Demand Training

In this learning path you will learn how to use the Visualizer Debug Environment to verify your design.

Chapters include:

  • Chapter 1 - Introduction to Visualizer
  • Chapter 2 - Visualizer GUI
  • Chapter 3 - Visualizer Commands
  • Chapter 4 - Debugging UVM Testbench

Learn more.

UVM Debug Course

UVM Debug Editor Insight

Verification Academy Editor Insight Session | Subject Matter Expert - Harry Foster | UVM Debug Course

This editor insight session provides an historical perspective on the origin of the word debugging, followed by a discussion on industry trends that motivated us to create our new UVM debug course.

UVM Connectivity Debug

UVM Connectivity Debug Session | Subject Matter Expert - Tom Kiley | UVM Debug Course

In this session we will discuss how to debug connectivity issues between UVM components using the UVM Schematic viewer.

UVM Phase Debug

UVM Phase Debug Session | Subject Matter Expert - Tom Kiley | UVM Debug Course

In this session we will provide an overview of UVM phases, some of the common issues that users run into, and methods to effectively debug them.

Memory Leak Debug

Memory Leak Debug Session | Subject Matter Expert - Tom Kiley | UVM Debug Course

In this session we will describe what a memory leak is in a UVM environment and how to effectively debug the issue.

UVM Configuration Database Debug

UVM Configuration Database Debug Session | Subject Matter Expert - Tom Kiley | UVM Debug Course

In this session we will provide an overview of the UVM configuration database, discuss some of the common issues with configurations, and methods to debug them.

Featured Sessions

Prevent Performance Problems with Prompt RTL Profiling

Prevent Performance Problems with Prompt RTL Profiling | Rich Edelman

In this session, we will show how you can employ this capability from the software world to optimize Verilog, SystemVerilog, or VHDL code for RTL simulations.

Accelerate Development Using Advanced Debugging Approaches

Accelerate Development Using Advanced Debugging Approaches | Subject Matter Expert - Rich Edelman | Aerospace and Defense Verification Tech Day

Visualizer Debug Environment provides a high-performance, high-capacity, tightly integrated debug environment for Simulation and Emulation. Waveform debug and source and connectivity debug for Verilog and VHDL are tightly integrated with class debug and UVM debug, with transaction viewing. Visualizer supports SystemVerilog, SystemC, C++ and C environments in the same way.

I Didn’t Know Visualizer Could Do That

I Didn’t Know Visualizer Could Do That Session | Rich Edelman

In this session, you will learn about Visualizer's powerful features that improve debug productivity for System Verilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.

Visualizer Coverage: Debug and Visualize All Your Coverage

Visualizer Coverage: Debug and Visualize All Your Coverage Without Leaving Your House – Even If You Can Session | Athira Panicker - Subject Matter Expert

In this session, you will learn coverage techniques including; how to use testplan tracker in Visualizer to analyze the testplan, finding uncovered items using code and functional coverage windows and fixing them using coverage debugging mode.

Embedded Software Debug Using Codelink and Visualizer

Embedded Software Debug Using Integrated Codelink and Visualizer HW/SW Debug Environment Session | Tomasz Piekarz - Subject Matter Expert

In this session, you will learn how you can save time and improve your embedded software debug techniques by utilizing tips and tricks in Post simulation.

Interactive Debug Techniques for UVM, SystemVerilog and RTL using Visualizer

Interactive Debug Techniques for UVM, SystemVerilog and RTL using Visualizer Session | Jason Polychronopoulos - Subject Matter Expert

This session will cover different techniques for debugging SystemVerilog UVM testbench and RTL source code while running a live simulation.

Introduction to Visualizer for the VHDL Users

Introduction to Visualizer for the VHDL Users Session | Subject Matter Expert - Rich Edelman | Visualizer Debug Environment: 3 Part Web Seminar Series

This session will introduce the Visualizer Debug Environment for VHDL and UVM.

Introduction to Visualizer for the Verilog Users

Introduction to Visualizer for the Verilog Users Session | Subject Matter Expert - Rich Edelman | Visualizer Debug Environment: 3 Part Web Seminar Series

This session will introduce the Visualizer Debug Environment for Verilog and UVM.

Better UVM Debug with Visualizer

Better UVM Debug with Visualizer Session | Subject Matter Expert - Rich Edelman | Visualizer Debug Environment: 3 Part Web Seminar Series

In this session you will learn UVM Debug tips and tricks in both Post simulation and Live simulation.

Context-Aware Debug for Complex Heterogeneous Environments

Context-Aware Debug for Complex Heterogeneous Environments Session | Subject Matter Expert - Rich Edelman | What’s New in Functional Verification from Mentor Web Seminar

In this session, you will learn how to utilize Visualizer to tackle complex UVM testbench challenges in Post (Class in waveform, schematic view …) and Live Sim mode (breakpoints …).

Transaction Recording & Debug with Questa & Visualizer

U2U Silicon Valley 2019 | Transaction Recording & Debug with Questa & Visualizer

This session will explore the Transaction Recording (TR) and debug capabilities of Questa Sim and how they can be applied in the context of a UVM testbench.

Resources

  • Articles
  • Blog Posts
  • Demos
  • White Papers
  • On Demand
  • News

Featured Debug Verification Horizons Articles

  • Getting to Know Visualizer, Part II
  • Getting to Know Visualizer, Part I
  • Questa Visualizer Adds Coverage Analysis to the Platform
  • Parallel Debug: A Path to a Better Big Data Diaspora
  • Certus™ Silicon Debug: Don't Prototype Without It
  • On-Chip Debug – Reducing Overall ASIC Development Schedule Risk
  • Increase Verification Productivity with Questa® UVM Debug
  • Visualizer™ Debug Environment: Class-based Testbench Debugging using a New School Debugger – Debug This!

Featured Debug Blog Posts

  • Finding Data
  • Verilog & VHDL Debug & Weeding
  • A UVM Scoreboard: Does it really have to be that hard?
  • Debugging SoCs Can Be Complicated
  • Why Is My Coverage The Way It Is?
  • Finding FUN – DPI-C Recording C Variables in a Wave Database
  • The UVM : Is it Safe?
  • Straight-up Smash-mouth Debug
  • So You Want a Different UVM Report Server. Doesn’t Everyone? Where To Start…
  • Debugging Complex UVM Testbenches
  • Debugging My UVM Factory and UVM Config
  • UVM Debug. A contest using class based testbench debug…
  • SystemVerilog Testbench Debug – Are we having fun yet?

Featured Debug Demos

Find bugs faster in the Visualizer™ Debug Environment, a high-performance, high-capacity debugger. Tightly integrated with both Questa® Simulation and Veloce® Emulation, Visualizer provides a full set of synchronized views that analyze waveforms, source code, connectivity and more for Verilog, SystemVerilog, VHDL and SystemC. In addition to being very intuitive and easy to use, Visualizer has several powerful features that improve debug productivity for SystemVerilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.

Features

  • Automatic X Tracing in Your Design
  • Wave Windows Features
  • FSM Viewer
  • Driver and Receiving Tracing
  • Design Exploration with the Advanced Search Window
  • Adding Signals to the Wave Window

Debugging Testbench in Interactive Mode

The following videos cover major features of Visualizer Interactive Mode. It might be useful to view them in the following order:

  • Part 1: Invoking Visualizer
  • Part 2: Intro to Commonly Used Windows
  • Part 3: Set Breakpoints and Single Step Debug
  • Part 4: Viewing Data Values
  • Part 5: Navigating a UVM Testbench
  • Part 6: Navigation with Class and File Views
  • Part 7: RTL Interactive Debug
  • Part 8: Checkpoint/Restore

Featured Debug White Paper

  • Questa Visualizer adds coverage analysis to the platform
  • The Big Brain Theory: Visualizing SoC Design and Verification Data
  • Full-Featured SOC Debug Cross-Triggering

Featured Debug On-Demand Technical Sessions

  • Prevent Performance Problems with Prompt RTL Profiling
  • Accelerate Development Using Advanced Debugging Approaches
  • I Didn't Know Visualizer Could That
  • Embedded Software Debug Using Codelink and Visualizer
  • Visualizer Coverage: Debug and Visualize All Your Coverage
  • Interactive Debug Techniques for UVM, SystemVerilog and RTL using Visualizer
  • Introduction to Visualizer for the VHDL Users
  • Introduction to Visualizer for the Verilog Users
  • Better UVM Debug with Visualizer
  • Transaction Recording & Debug with Questa & Visualizer
  • Productive Low Power Debug Across All Engines and Flows
  • Are You Trapped in an Unfamiliar, Large SystemVerilog UVM Testbench?
  • Enterprise Debug for Simulation
  • Improving UVM Testbench Debug Productivity and Visibility
  • UVM Debug Made Easy – Map, Trace, Track, Find and Fix Bugs
  • Evolution of Debug
  • Verification and Debug: Old School Meets New School
  • Advanced UVM Debug
  • UVM Debug
  • Advanced Debugging with Assertions
  • Questa® Power Aware Visualizer Demo

Featured Debug News & Press

  • Context-Aware Debug
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