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  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

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      • Coverage Forum

    • Additional Forums

      • Announcements
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      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Debug with Codelink and Visualizer - December 8th
      • U2U MARLUG - January 26th
      • Events Calendar

    • On Demand Seminars

      • I'm Excited About Formal...My Journey From Skeptic To Believer
      • Interactive Debug Techniques
      • Formal-based ‘X’ Verification
      • 2020 Functional Verification Study
      • All On-Demand Seminars

    • Recording Archive

      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
      • All Recordings

    • Mentor Training Center

      • SystemVerilog for Verification
      • SystemVerilog UVM
      • UVM Framework
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • Questa Simulation Coverage Acceleration Apps with inFact
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
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      • Academy Newsletter
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    • Verification Horizons Publication

      • Verification Horizons - November 2020
      • Verification Horizons - July 2020
      • Verification Horizons - March 2020
      • Issue Archive

    • About Us

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    • Training

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      • Functional Verification Library
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  • Debug

Debug

Debug

Debug takes a significant proportion of any design or verification engineer’s time. An Intuitive and powerful HW and SW debug solution is needed to improve debug productivity across ESL, formal, RTL/gate-level simulation and emulation platforms. In addition to being intuitive and easy to use, a debug methodology needs several powerful attributes that improve debug productivity for SystemVerilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.

Below please find the UVM Debug course, on demand seminars covering tracing, adding signals and more plus sessions on Visualizer™ Debug Environment to get you started.

Upcoming Visualizer Web Seminars

Visualizer Coverage: Debug and Visualize All Your Coverage Without Leaving Your House – Even If You Can

  • Thursday, November 19th, 2020
  • 8:00 AM - 9:00 AM US/Pacific

Embedded Software Debug Using Integrated Codelink and Visualizer HW/SW Debug Environment

  • Tuesday, December 8th, 2020
  • 8:00 AM - 9:00 AM US/Pacific

UVM Debug Course

UVM Debug Editor Insight

Verification Academy Editor Insight Session | Subject Matter Expert - Harry Foster | UVM Debug Course

This editor insight session provides an historical perspective on the origin of the word debugging, followed by a discussion on industry trends that motivated us to create our new UVM debug course.

UVM Connectivity Debug

UVM Connectivity Debug Session | Subject Matter Expert - Tom Kiley | UVM Debug Course

In this session we will discuss how to debug connectivity issues between UVM components using the UVM Schematic viewer.

UVM Phase Debug

UVM Phase Debug Session | Subject Matter Expert - Tom Kiley | UVM Debug Course

In this session we will provide an overview of UVM phases, some of the common issues that users run into, and methods to effectively debug them.

Memory Leak Debug

Memory Leak Debug Session | Subject Matter Expert - Tom Kiley | UVM Debug Course

In this session we will describe what a memory leak is in a UVM environment and how to effectively debug the issue.

UVM Configuration Database Debug

UVM Configuration Database Debug Session | Subject Matter Expert - Tom Kiley | UVM Debug Course

In this session we will provide an overview of the UVM configuration database, discuss some of the common issues with configurations, and methods to debug them.

Featured Sessions

Interactive Debug Techniques for UVM, SystemVerilog and RTL using Visualizer

Interactive Debug Techniques for UVM, SystemVerilog and RTL using Visualizer Session | Jason Polychronopoulos - Subject Matter Expert

Visualizer provides an advanced debug environment that includes many tools to help with both post-simulation and live-simulation debug. This session will cover different techniques for debugging SystemVerilog UVM testbench and RTL source code while running a live simulation.

Better UVM Debug with Visualizer

Better UVM Debug with Visualizer Session | Subject Matter Expert - Rich Edelman | Visualizer Debug Environment: 3 Part Web Seminar Series

Find problems in your UVM testbench faster using Visualizer Debug Environment, a high-performance, high-capacity debugger. UVM testbenches can be intuitively debugged in either interactive simulation or post simulation. You will see UVM Objects, UVM Components, Class Instances, transactions and more. In this session you will learn UVM Debug tips and tricks in both Post simulation and Live simulation.

Introduction to Visualizer for the VHDL Users

Introduction to Visualizer for the VHDL Users Session | Subject Matter Expert - Rich Edelman | Visualizer Debug Environment: 3 Part Web Seminar Series

Complex testing and methodology with complex silicon require powerful but simple to use debug solutions. The Visualizer Debug Environment provides a common debug solution for simulation, emulation and other engines, including Verilog, VHDL, UVM, SystemC, C/C++, Assertions and Coverage. This session will introduce the Visualizer Debug Environment for VHDL and UVM.

Introduction to Visualizer for the Verilog Users

Introduction to Visualizer for the Verilog Users Session | Subject Matter Expert - Rich Edelman | Visualizer Debug Environment: 3 Part Web Seminar Series

Complex testing and methodology with complex silicon require powerful but simple to use debug solutions. The Visualizer Debug Environment provides a common debug solution for simulation, emulation and other engines, including Verilog, VHDL, UVM, SystemC, C/C++, Assertions and Coverage. This session will introduce the Visualizer Debug Environment for Verilog and UVM.

Context-Aware Debug for Complex Heterogeneous Environments

Context-Aware Debug for Complex Heterogeneous Environments Session | Subject Matter Expert - Rich Edelman | What’s New in Functional Verification from Mentor Web Seminar

In this session, you will learn how to utilize Visualizer to tackle complex UVM testbench challenges in Post (Class in waveform, schematic view …) and Live Sim mode (breakpoints …).

Transaction Recording & Debug with Questa & Visualizer

U2U Silicon Valley 2019 | Transaction Recording & Debug with Questa & Visualizer

This session will explore the Transaction Recording (TR) and debug capabilities of Questa Sim and how they can be applied in the context of a UVM testbench.

Resources

  • Articles
  • Success Stories
  • Blog Posts
  • Demos
  • White Papers
  • On Demand
  • News
  • Product Information

Featured Debug Verification Horizons Articles

  • Parallel Debug: A Path to a Better Big Data Diaspora
  • Certus™ Silicon Debug: Don't Prototype Without It
  • On-Chip Debug – Reducing Overall ASIC Development Schedule Risk
  • Increase Verification Productivity with Questa® UVM Debug
  • Visualizer™ Debug Environment: Class-based Testbench Debugging using a New School Debugger – Debug This!

Featured Debug Success Stories:

  • Visualizer™ Debug Environment reduces Debug time and Increases Productivity for Brocade®
  • Adding Clarity to the Debug Picture at Pixelworks

Featured Debug Blog Posts

  • Straight-up Smash-mouth Debug
  • Debugging Complex UVM Testbenches
  • Debugging My UVM Factory and UVM Config
  • UVM Debug. A contest using class based testbench debug…
  • SystemVerilog Testbench Debug – Are we having fun yet?

Featured Debug Demos

Find bugs faster in the Visualizer™ Debug Environment, a high-performance, high-capacity debugger. Tightly integrated with both Questa® Simulation and Veloce® Emulation, Visualizer provides a full set of synchronized views that analyze waveforms, source code, connectivity and more for Verilog, SystemVerilog, VHDL and SystemC. In addition to being very intuitive and easy to use, Visualizer has several powerful features that improve debug productivity for SystemVerilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.

Features

  • Automatic X Tracing in Your Design
  • Wave Windows Features
  • FSM Viewer
  • Driver and Receiving Tracing
  • Design Exploration with the Advanced Search Window
  • Adding Signals to the Wave Window

Debugging Testbench in Interactive Mode

The following videos cover major features of Visualizer Interactive Mode. It might be useful to view them in the following order:

  • Part 1: Invoking Visualizer
  • Part 2: Intro to Commonly Used Windows
  • Part 3: Set Breakpoints and Single Step Debug
  • Part 4: Viewing Data Values
  • Part 5: Navigating a UVM Testbench
  • Part 6: Navigation with Class and File Views
  • Part 7: RTL Interactive Debug
  • Part 8: Checkpoint/Restore

Featured Debug White Paper

  • The Big Brain Theory: Visualizing SoC Design and Verification Data
  • Full-Featured SOC Debug Cross-Triggering

Featured Debug On-Demand Technical Sessions

  • Interactive Debug Techniques for UVM, SystemVerilog and RTL using Visualizer
  • Introduction to Visualizer for the VHDL Users
  • Introduction to Visualizer for the Verilog Users
  • Better UVM Debug with Visualizer
  • Transaction Recording & Debug with Questa & Visualizer
  • Productive Low Power Debug Across All Engines and Flows
  • Are You Trapped in an Unfamiliar, Large SystemVerilog UVM Testbench?
  • Enterprise Debug for Simulation
  • Improving UVM Testbench Debug Productivity and Visibility
  • UVM Debug Made Easy – Map, Trace, Track, Find and Fix Bugs
  • Evolution of Debug
  • Verification and Debug: Old School Meets New School
  • Advanced UVM Debug
  • UVM Debug
  • Advanced Debugging with Assertions
  • Questa® Power Aware Visualizer Demo

Featured Debug News & Press

  • Context-Aware Debug

High Performance Debug Environment for Digital Design and Verification

Intuitive and easy to use, Visualizer™ Debug Environment automates debugging for the digital design and verification of today's complex SoCs and FPGAs.

Find bugs faster in the Visualizer Debug Environment, a high-performance, high-capacity debugger. Tightly integrated with both Questa Simulation and Veloce Emulation, it provides a full set of synchronized views that analyze waveforms, source code, connectivity and more for Verilog, SystemVerilog and VHDL. In addition to being very intuitive and easy to use, Visualizer has several powerful features that improve debug productivity for SystemVerilog/UVM, transaction-level, RTL, gate-level and low-power design and verification..

Learn more | Datasheet

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