Find bugs faster in the Visualizer™ Debug Environment, a high-performance, high-capacity debugger. Tightly integrated with both Questa® Simulation and Veloce® Emulation, Visualizer provides a full set of synchronized views that analyze waveforms, source code, connectivity and more for Verilog, SystemVerilog, VHDL and SystemC. In addition to being very intuitive and easy to use, Visualizer has several powerful features that improve debug productivity for SystemVerilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.
Features
Debugging Testbench in Interactive Mode
The following videos cover major features of Visualizer Interactive Mode. It might be useful to view them in the following order: