High Performance Debug Environment for Digital Design and Verification
Intuitive and easy to use, Visualizer™ Debug Environment automates debugging for the digital design and verification of today's complex SoCs and FPGAs.
Find bugs faster in the Visualizer Debug Environment, a high-performance, high-capacity debugger. Tightly integrated with both Questa Simulation and Veloce Emulation, it provides a full set of synchronized views that analyze waveforms, source code, connectivity and more for Verilog, SystemVerilog and VHDL. In addition to being very intuitive and easy to use, Visualizer has several powerful features that improve debug productivity for SystemVerilog/UVM, transaction-level, RTL, gate-level and low-power design and verification..
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