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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • UVMF - One Bite at a Time
      • Introduction to UVM
      • Basic UVM
      • UVM Debug
      • Advanced UVM
      • UVM Connect

    • Featured Courses

      • Introduction to DO-254
      • Portable Stimulus Basics
      • SystemVerilog OOP for UVM Verification
      • Power Aware Verification
      • Power Aware CDC Verification
      • Assertion-Based Verification
      • Metrics in SoC Verification

    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal Coverage
      • Formal-Based Technology: Automatic Formal Solutions
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
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      • No Replies
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      • UVM Forum

    • SystemVerilog Forum

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    • Coverage Forum

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      • Coverage Forum

    • Additional Forums

      • Announcements
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      • AMS Forum
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizon - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • DVCon - February 25th
      • Maximizing Debug Productivity - February 27th
      • Events Calendar

    • On Demand Seminars

      • Low Power Verification Forum
      • Portable Simulus
      • Debug
      • FPGA Verification
      • Stimulus Generation
      • UVM Forum
      • All On-Demand Seminars

    • Recording Archive

      • Portable Stimulus from IP to SoC
      • UVM 1800.2 & Updated UVM Cookbook
      • Wilson Research Group - 2018 Results
      • What Is Formal, And How It Works Under-the-Hood
      • DAC & DVCon
      • All Recordings

    • Mentor Training Center

      • SystemVerilog Assertions
      • SystemVerilog for Verification
      • SystemVerilog UVM
      • SystemVerilog UVM Advanced
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Vectors and Arrays
      • SystemVerilog Advanced OOP
      • SystemVerilog Functional Coverage
      • UVM Transactions and Sequences
      • UVM Monitors and Agents
      • UVM Tests and Complex Sequences
      • Functional Verification Library
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - November 2018
      • Verification Horizons - June 2018
      • Verification Horizons - March 2018
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • SystemVerilog
      • Functional Verification Library
  • Home /
  • Debug

Debug

Debug

Debug takes a significant proportion of any design or verification engineer’s time. An Intuitive and powerful HW and SW debug solution is needed to improve debug productivity across ESL, formal, RTL/gate-level simulation and emulation platforms. In addition to being intuitive and easy to use, a debug methodology needs several powerful attributes that improve debug productivity for SystemVerilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.

Below please find the UVM Debug course, on demand seminars covering tracing, adding signals and more plus sessions on the Visualizer™ Debug Environment to get you started.

UVM Debug Course

Design complexity continues to increase, which is contributing to new challenges in verification and debug. Fortunately, new solutions and methodologies (such as UVM) have emerged to address growing design complexity. Yet, even with the productivity gains that can be achieved with the adoption of UVM, newer debugging challenges specifically related to UVM need to be addressed.

In UVM Debug course, we examine common UVM debug issues, and provide a systematic set of recommendations to effectively address them.

Sessions

UVM Debug Editor Insight

Verification Academy Editor Insight Session | Subject Matter Expert - Harry Foster | UVM Debug Course

This editor insight session provides an historical perspective on the origin of the word debugging, followed by a discussion on industry trends that motivated us to create our new UVM debug course.

UVM Connectivity Debug

UVM Connectivity Debug Session | Subject Matter Expert - Tom Kiley | UVM Debug Course

In this session we will discuss how to debug connectivity issues between UVM components using the UVM Schematic viewer.

UVM Phase Debug

UVM Phase Debug Session | Subject Matter Expert - Tom Kiley | UVM Debug Course

In this session we will provide an overview of UVM phases, some of the common issues that users run into, and methods to effectively debug them.

Memory Leak Debug

Memory Leak Debug Session | Subject Matter Expert - Tom Kiley | UVM Debug Course

In this session we will describe what a memory leak is in a UVM environment and how to effectively debug the issue.

UVM Configuration Database Debug

UVM Configuration Database Debug Session | Subject Matter Expert - Tom Kiley | UVM Debug Course

In this session we will provide an overview of the UVM configuration database, discuss some of the common issues with configurations, and methods to debug them.

Upcoming Sessions:

  • Debugging UVM Scoreboards
  • Debugging Objections
  • Using Breakpoints for UVM Debug
  • UVM PostSim Debug in Wave Window

Debug Resources

Success Stories:

  • Visualizer™ Debug Environment reduces Debug time and Increases Productivity for Brocade®
  • Adding Clarity to the Debug Picture at Pixelworks

Articles:

  • Parallel Debug: A Path to a Better Big Data Diaspora
  • Certus™ Silicon Debug: Don't Prototype Without It
  • On-Chip Debug – Reducing Overall ASIC Development Schedule Risk
  • Increase Verification Productivity with Questa® UVM Debug
  • Visualizer Debug Environment: Class-based Testbench Debugging using a New School Debugger – Debug This!

Technical Paper:

  • Debug This! Class-based testbench debugging with Visualizer

Sessions

Are You Trapped in an Unfamiliar, Large SystemVerilog UVM Testbench?

Are You Trapped In an Unfamiliar, Large SystemVerilog UVM Testbench? | User2User - Munich 2017

This session will describe useful debug techniques for debugging a UVM testbench with 8 to 10 agents, and many stimulus generators, checkers and exception handlers running in parallel.

Improving UVM Testbench Debug Productivity and Visibility

Improving UVM Testbench Debug Productivity and Visibility Session | Subject Matter Expert - Gordon Allan | UVM Forum Seminar

Learn how to solve the top 10 common UVM bring up issues with the config_db, the factory, and sequence execution.

UVM Debug Made Easy – Map, Trace, Track, Find and Fix Bugs

DAC 2016 | UVM Debug Made Easy – Map, Trace, Track, Find and Fix Bugs

In this session, you will learn how to solve the top 10 common UVM bringup issues in areas such as the config_db, the factory, and sequence execution and more.

Visualizer™ Debug Environment

Find bugs faster in the Visualizer Debug Environment, a high-performance, high-capacity debugger. Tightly integrated with both Questa Simulation and Veloce Emulation, it provides a full set of synchronized views that analyze waveforms, source code, connectivity and more for Verilog, SystemVerilog, VHDL and SystemC. In addition to being very intuitive and easy to use, Visualizer has several powerful features that improve debug productivity for SystemVerilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.

Features

  • Automatic X Tracing in Your Design
  • Wave Windows Features
  • FSM Viewer
  • Driver and Receiving Tracing
  • Design Exploration with the Advanced Search Window
  • Adding Signals to the Wave Window

Debugging Testbench in Interactive Mode

The following videos cover major features of Visualizer Interactive Mode. It might be useful to view them in the following order:

  • Part 1: Invoking Visualizer
  • Part 2: Intro to Commonly Used Windows
  • Part 3: Set Breakpoints and Single Step Debug
  • Part 4: Viewing Data Values
  • Part 5: Navigating a UVM Testbench
  • Part 6: Navigation with Class and File Views
  • Part 7: RTL Interactive Debug
  • Part 8: Checkpoint/Restore

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