Debug | Verification Academy

UVM Debug Course

UVM Debug Editor Insight

This editor insight session provides an historical perspective on the origin of the word debugging, followed by a discussion on industry trends that motivated us to create our new UVM debug course.

UVM Connectivity Debug

In this session we will discuss how to debug connectivity issues between UVM components using the UVM Schematic viewer.

UVM Phase Debug

In this session we will provide an overview of UVM phases, some of the common issues that users run into, and methods to effectively debug them.

Memory Leak Debug

In this session we will describe what a memory leak is in a UVM environment and how to effectively debug the issue.

UVM Configuration Database Debug

In this session we will provide an overview of the UVM configuration database, discuss some of the common issues with configurations, and methods to debug them.

Featured Sessions

Accelerate Development Using Advanced Debugging Approaches

Visualizer Debug Environment provides a high-performance, high-capacity, tightly integrated debug environment for Simulation and Emulation. Waveform debug and source and connectivity debug for Verilog and VHDL are tightly integrated with class debug and UVM debug, with transaction viewing. Visualizer supports SystemVerilog, SystemC, C++ and C environments in the same way.

I Didn’t Know Visualizer Could Do That

In this session, you will learn about Visualizer's powerful features that improve debug productivity for System Verilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.

Visualizer Coverage: Debug and Visualize All Your Coverage

In this session, you will learn coverage techniques including; how to use testplan tracker in Visualizer to analyze the testplan, finding uncovered items using code and functional coverage windows and fixing them using coverage debugging mode.

Embedded Software Debug Using Codelink and Visualizer

In this session, you will learn how you can save time and improve your embedded software debug techniques by utilizing tips and tricks in Post simulation.

Interactive Debug Techniques for UVM, SystemVerilog and RTL using Visualizer

This session will cover different techniques for debugging SystemVerilog UVM testbench and RTL source code while running a live simulation.

Introduction to Visualizer for the VHDL Users

This session will introduce the Visualizer Debug Environment for VHDL and UVM.

Introduction to Visualizer for the Verilog Users

This session will introduce the Visualizer Debug Environment for Verilog and UVM.

Better UVM Debug with Visualizer

In this session you will learn UVM Debug tips and tricks in both Post simulation and Live simulation.

Context-Aware Debug for Complex Heterogeneous Environments

In this session, you will learn how to utilize Visualizer to tackle complex UVM testbench challenges in Post (Class in waveform, schematic view …) and Live Sim mode (breakpoints …).

Transaction Recording & Debug with Questa & Visualizer

This session will explore the Transaction Recording (TR) and debug capabilities of Questa Sim and how they can be applied in the context of a UVM testbench.

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