Hi There, I’m doing a test with UVM, and the reference model is written with SystemC, and UVMC is used to connect UVM and SystemC. The simulator is Synopsis VCS. When I run the test, the simulation time is always stuck at 0, and there are 2 caught UVM_FATAL reports which I can’t see the details. Pls find log for details.
[root@ws btopc_sysc]# make sim
rm -rf DVEfiles csrc simv simv.daidir ucli.key .vlogansetup.args .vlogansetup.env .vcs_lib_lock simv.vdb AN.DB vc_hdrs.h *.diag *.vpd *tar.gz external.o
# /usr/local/bin/g++ -c src/ref/external.cpp -o external.o
syscan -full64 -cpp /usr/local/bin/g++ -cc /usr/local/bin/gcc -tlm2 -cflags "-g -I. -I/home/tools/vcs/T-2022.06-SP1-1/linux64/suse/etc/systemc/tlm/tli -I/home/tools/uvmc/uvmc-2.3.2//src/connect/sc" /home/tools/uvmc/uvmc-2.3.2//src/connect/sc/uvmc.cpp /home/tools/vcs/T-2022.06-SP1-1/linux64/rhel/etc/uvm/src/dpi/uvm_dpi.cc ./src/ref//sys_top.cpp -CFLAGS -DVCS
vlogan -full64 -q -sverilog -ntb_opts uvm -timescale=1ps/1ps +define+UVM_OBJECT_MUST_HAVE_CONSTRUCTOR +incdir+/home/tools/vcs/T-2022.06-SP1-1/linux64/rhel/etc/uvm/src+/home/tools/vcs/T-2022.06-SP1-1/linux64/rhel/etc/uvm/src/vcs+/home/tools/uvmc/uvmc-2.3.2//src/connect/sv +define+UVM_OBJECT_MUST_HAVE_CONSTRUCTOR /home/tools/vcs/T-2022.06-SP1-1/linux64/rhel/etc/uvm/src/uvm_pkg.sv /home/tools/uvmc/uvmc-2.3.2//src/connect/sv/uvmc_pkg.sv /home/tools/vcs/T-2022.06-SP1-1/linux64/rhel/etc/uvm/src/dpi/uvm_dpi.cc -f filelist/filelist.f -ntb_opts uvm +define+UVM_REG_DATA_WIDTH=128
Warning-[IPDASP] Identifier in ANSI port declaration
src/tb/adder.sv, 2
Redeclaration of ANSI ports not allowed for 'state', this will be an error
in a future release
Note-[SV-LCM-PPWI] Package previously wildcard imported
src/tb/top.sv, 1
$unit
Package 'uvm_pkg' already wildcard imported.
Ignoring uvm_pkg::*
See the SystemVerilog LRM(1800-2005), section 19.2.1.
vcs -full64 -q -sysc=adjust_timeres -lca -sysc sc_main top -top top -debug_access+all -timescale=1ps/1ps
Warning-[LCA_FEATURES_ENABLED] Usage warning
LCA features enabled by '-lca' argument on the command line. For more
information regarding list of LCA features please refer to Chapter "LCA
features" in the VCS Release Notes
Doing common elaboration
Notice: Ports coerced to inout, use -notice for details
9 modules and 0 UDP read.
make[1]: Entering directory '/my_prj/sysc/uvmsysc/btopc_sysc/csrc'
make[1]: Leaving directory '/my_prj/sysc/uvmsysc/btopc_sysc/csrc'
make[1]: Entering directory '/my_prj/sysc/uvmsysc/btopc_sysc/csrc'
gcc -w -pipe -O -I/home/tools/vcs/T-2022.06-SP1-1/linux64/suse/include -fPIC -fPIC -c -o uM9F1_0x2aB.o uM9F1_0x2aB.c
../simv_elab up to date
make[1]: Leaving directory '/my_prj/sysc/uvmsysc/btopc_sysc/csrc'
/home/tools/vcs/T-2022.06-SP1-1/linux64/suse/bin/vcs: line 34499: 242178 Segmentation fault (core dumped) ${TOOL_HOME}/bin/cfs_ident_exec -f ${XML_INPUT_EXE} -o "${fsearchDir}/idents_tapi.xml" -o_SrcFile "${dirSrcFiles}/src_files_c" ${all_dyn_libs} > tapi_xml_writer.log
Connecting an SC-side proxy chan for 'refmod_i.in' with lookup string 'refmod_i.in' for later connection with SV
Connecting an SC-side proxy chan for 'refmod_i.out' with lookup string 'refmod_i.out' for later connection with SV
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP1-1_Full64; Runtime version T-2022.06-SP1-1_Full64; Jun 24 11:22 2025
----------------------------------------------------------------
UVM-1.1d.Synopsys
(C) 2007-2013 Mentor Graphics Corporation
(C) 2007-2013 Cadence Design Systems, Inc.
(C) 2006-2013 Synopsys, Inc.
(C) 2011-2013 Cypress Semiconductor Corp.
----------------------------------------------------------------
*********** IMPORTANT RELEASE NOTES ************
You are using a version of the UVM library that has been compiled
with `UVM_NO_DEPRECATED undefined.
See http://www.eda.org/svdb/view.php?id=3313 for more details.
(Specify +UVM_NO_RELNOTES to turn off this notice)
Warning-[LCA_FEATURES_ENABLED] Usage warning
LCA features enabled by '-lca' argument on the command line. For more
information regarding list of LCA features please refer to Chapter "LCA
features" in the VCS Release Notes
Doing common elaboration
Notice: Ports coerced to inout, use -notice for details
11 modules and 0 UDP read.
make[1]: Entering directory '/my_prj/sysc/uvmsysc/btopc_sysc/csrc'
make[1]: Leaving directory '/my_prj/sysc/uvmsysc/btopc_sysc/csrc'
make[1]: Entering directory '/my_prj/sysc/uvmsysc/btopc_sysc/csrc'
../simv up to date
make[1]: Leaving directory '/my_prj/sysc/uvmsysc/btopc_sysc/csrc'
/home/tools/vcs/T-2022.06-SP1-1/linux64/suse/bin/vcs: line 34499: 243789 Segmentation fault (core dumped) ${TOOL_HOME}/bin/cfs_ident_exec -f ${XML_INPUT_EXE} -o "${fsearchDir}/idents_tapi.xml" -o_SrcFile "${dirSrcFiles}/src_files_c" ${all_dyn_libs} > tapi_xml_writer.log
Connecting an SC-side proxy chan for 'refmod_i.in' with lookup string 'refmod_i.in' for later connection with SV
Connecting an SC-side proxy chan for 'refmod_i.out' with lookup string 'refmod_i.out' for later connection with SV
./simv +UVM_TR_RECORD +UVM_VERBOSITY=HIGH +UVM_TESTNAME=simple_test -sysc=stackguardsize:200M
Warning-[SC-STACK-RANGE] Stack size range
The specified 'stack guard' size value is greater than 1M. The value is
accepted, but please be aware of extra memory and performance costs.
If you want to have another size, please change the size value and restart
the simulation.
Connecting an SC-side proxy chan for 'refmod_i.in' with lookup string 'refmod_i.in' for later connection with SV
Connecting an SC-side proxy chan for 'refmod_i.out' with lookup string 'refmod_i.out' for later connection with SV
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP1-1_Full64; Runtime version T-2022.06-SP1-1_Full64; Jun 24 11:22 2025
----------------------------------------------------------------
UVM-1.1d.Synopsys
(C) 2007-2013 Mentor Graphics Corporation
(C) 2007-2013 Cadence Design Systems, Inc.
(C) 2006-2013 Synopsys, Inc.
(C) 2011-2013 Cypress Semiconductor Corp.
----------------------------------------------------------------
*********** IMPORTANT RELEASE NOTES ************
You are using a version of the UVM library that has been compiled
with `UVM_NO_DEPRECATED undefined.
See http://www.eda.org/svdb/view.php?id=3313 for more details.
(Specify +UVM_NO_RELNOTES to turn off this notice)
UVM_INFO src/tb/top.sv(28) @ 0: reporter [top] Start Dumping
*Verdi* Loading libsscore_vcs202206.so
*Verdi* : Loading SystemC dumping library libsscore_vcs202206_sc233_gcc920.so.
FSDB Dumper for VCS, Release Verdi_T-2022.06-SP1-1, Linux x86_64/64bit, 10/16/2022
(C) 1996 - 2022 by Synopsys, Inc.
*Verdi* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi* : Create FSDB file 'top.fsdb'
*Verdi* : Begin traversing the scope (top), layer (0).
*Verdi* : End of traversing.
*Verdi* : Begin traversing the scopes, layer (0).
*Verdi* : Enable +struct dumping.
*Verdi* : End of traversing.
*Verdi* : Begin traversing the scopes, layer (0).
*Verdi* : Enable +mda dumping.
*Verdi* : End of traversing.
*Verdi* : Begin traversing the scopes, layer (0).
*Verdi* : Enable +all dumping.
*Verdi* WARNING: Option +all, +sc_plain or +sc_struct may have performance impact in SystemC dumping process. Use the following methods to minimize the impact.
1) If plain member is not necessary.
a) If option +all is specified:
Remove this option and specify only necessary options.
b) If option +sc_plain is specified:
Remove this option.
2) If SystemC struct is not necessary.
a) If option +all is specified:
Remove this option and specify only necessary options.
b) If option +sc_struct is specified:
Remove this option.
3) If SystemC signal with user-defined-type needs to be dumped but plain member with user-defined-type is not necessary.
Example Signals:
sc_signal<user-defined-type> sig_with_userdef; --- (A)
sc_signal<int> sig_with_primitive; --- (B)
sc_fifo<user-defined-type> fifo_with_userdef; --- (C)
sc_fifo<int> fifo_with_primitive; --- (D)
user-defined-type plain_with_userdef; --- (E)
int plain_with_primitive; --- (F)
Option +sc_no_plain_rel can be used to filter out all plain members.
Example Usage:
Specify options +all and +sc_no_plain_rel:
(A)(B)(C)(D) will be dumped, but (E)(F) will not.
*Verdi* : End of traversing.
VCD+ Writer T-2022.06-SP1-1_Full64 Copyright (c) 1991-2022 by Synopsys Inc.
UVM_INFO @ 0: reporter [RNTST] Running test simple_test...
----------------------------------------------------------------
UVMC-2.3
(C) 2009-2014 Mentor Graphics Corporation
----------------------------------------------------------------
Registering SV-side 'from_refmod.put_export' and lookup string 'refmod_i.out' for later connection with SC
Registering SV-side 'uvm_test_top.env_h.to_refmod.get_peek_export' and lookup string 'refmod_i.in' for later connection with SC
Connected SC-side 'refmod_i.out' to SV-side 'from_refmod.put_export'
Connected SC-side 'refmod_i.in' to SV-side 'uvm_test_top.env_h.to_refmod.get_peek_export'
UVM_INFO src/tb/env.sv(43) @ 0: uvm_test_top.env_h [env] Reporting matched 0
--- UVM Report catcher Summary ---
Number of demoted UVM_FATAL reports : 0
Number of demoted UVM_ERROR reports : 0
Number of demoted UVM_WARNING reports: 0
Number of caught UVM_FATAL reports : 2
Number of caught UVM_ERROR reports : 0
Number of caught UVM_WARNING reports : 0
--- UVM Report Summary ---
** Report counts by severity
UVM_INFO : 3
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[env] 1
[top] 1
$finish called from file "/home/tools/vcs/T-2022.06-SP1-1/linux64/suse/etc/uvm/base/uvm_root.svh", line 437.
$finish at simulation time 0
V C S S i m u l a t i o n R e p o r t
Time: 0 ps
CPU Time: 0.560 seconds; Data structure size: 0.6Mb
Tue Jun 24 11:22:36 2025