UVM vs COCO TB for Verification

UVM
1

Hi All,

Which verification methodology is better coco tb or UVM, especially for a design containing some complex digital modules like FIR filters, ADC and analog modules?
Can anyone please throw some light on this? Also what are pros and cons of both coco tb and uvm?

Also how easy it is to integrate analog verification into UVM and coco tb?

Regards,
Abhinandan

2

I suppose you didn’t receive a response because the number of CocoTB users on this site is quite small, and the number of users who have a good grasp of both CocoTB and UVM is infinitesimal.

Also, you need to give us a clearer definition of what “better” means to you. Python is an excellent language for learning and experimentation, with a vast infrastructure supporting it compared to what’s available with UVM. However, when it comes to performance, Python is incredibly slow. This might not be a concern for you now, but it will become a significant issue in the future, making it difficult to address without starting over.

Is integrating a debug environment important to you? Do you need to see waveforms from your testbench and DUT together?

I could go on, but you can tell I’m pretty biased at this point. :slight_smile:

FYI, Accellera recently released the first version of UVM-MS at the beginning of this year.

2 Likes
3

Thanks for the response @dave_59 .

“Better” I meant in two ways:
One is the functional verification of a communication sub-system
Second, is if we want to verify the performance in terms of data rate.

So, keeping these two as criteria which is better?
Also, can we use both of them together? Or can we use one approach for functional and the other for performance?

Regards,
Abhinandan

4

Hi @dave_59 ,

Yes, integrating debug environment is important as I have verify functionally.

Regards,
Abhinandan

5

This link i 3 years old. Not much has changed.

https://www.reddit.com/r/FPGA/comments/v8fd63/cocotb_in_python_vs_uvm_in_systemverilog/

6

Thanks @dave_59