Visualizer: Livesim / Interactive
In this track, you will learn how Visualizer Debug Environment provides a full set of synchronized views that analyze waveforms, source code, connectivity and more for Verilog, SystemVerilog, VHDL and SystemC. In addition to being very intuitive and easy to use, Visualizer has several powerful features that improve debug productivity for SystemVerilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.
-
Sessions
-
Automatic X Tracing in Your Design
In this session we will discuss how to trace the source of the problem using Visualizer Time Cone view. -
Wave Windows Features
In this session, we will review the wave window features and and how you can leverage them in your debug activity. -
FSM Viewer
In this session we show how to debug FSM issues efficiently in Visualizer. -
Driver and Receiving Tracing
In this session we will discuss how Visualizer enables you to quickly trace drivers and receivers. -
Design Exploration with the Advanced Search Window
In this session, you will learn how to explore or search for objects in your design (memory, packages etc…) in Visualizer. -
Adding Signals to the Wave Window
In this session we will discuss the many ways you can add signals to the wave window in Visualizer. -
Invoking Visualizer
In this session, you will learn how to generate the design.bin file and invoke Visualizer in interactive mode. -
Commonly Used Windows
In this session, you will be introduced to the most common window layouts in Visualizer interactive debug. -
Set Breakpoints and Single Step Debug
In this session you will learn how to use breakpoints in the testbench and single step debug. -
Viewing Data Values
In this session, you will learn how to look for Values, browse, add to watchlist, VA & VT, add to local window. -
Navigating a UVM Testbench
In this session, you will learn how to navigate the testbench using UVM based hierarchy, sequence, threads and class instance. -
Navigation with Class and File Views
In this session, you will learn how to navigate the testbench using file, class and lexical search (non UVM). -
RTL Interactive Debug
In this session, you will learn how to view RTL data during interactive debug. -
Checkpoint/Restore
In this session, you will learn how to utilize checkpoint/restore during interactive debug. -
Navigate File Class
In this session, you will learn how to navigate the testbench using file, class and lexical search (non UVM). -
RTL in Interactive
In this session, you will learn how to view RTL data during interactive debug. -
BreakPoint and Step
In this session, you will learn how to set a breakpoint in the testbench and do single step debug. -
Questa Visualizer - Power Aware Debug
In this demo, you will learn the UPF based Power Aware Debug features available in Visualizer with Questa PASim.
-
-
Overview
The Visualizer Debug Environment is a graphical user interface (GUI) that provides a visual display of data obtained from a variety of simulation or emulation products. This display consists primarily of interactive windows that show contents and characteristics of the design such as signals, waveforms, schematic, hierarchy, HDL source, variables, assertions, memory usage, and finite state machines.
Capabilities of the Visualizer Debug Environment
Visualizer supports several types of debugging operations, such as the following:
- Tracing active drivers and receivers.
- Visual tracking of currently executing code in the Source Window.
- Causality analysis with the Time Cone window where you can visually trace an event (such as an X value) back to its source through multiple clocks.
- Time synchronization of multiple windows.
- Exploring and replaying SystemVerilog Assertions.
- Waveform debugging of design signals, class objects, and transactions.
- UVM-aware debugging—including hierarchy, sequences, threads, locals, and configuration.
- Profiling simulation performance to identify areas in your design where performance can be improved.
Key Concepts and Requirements
Note the following considerations for using the Visualizer Debug Environment:
- It is available only on a 64-bit Linux operating system.
- Its primary application is to provide a debugging environment (as a back-end GUI) for the Questa SIM simulator and the Veloce emulator. Consequently, the information in this manual is oriented toward usage with those Siemens EDA products.
Generally, you use the Visualizer Debug Environment in either of the following ways:
- Post-simulation mode — invoke Visualizer as a standalone application and view results from a previous simulation or emulation.
- Live-simulation mode — invoke Visualizer in conjunction with an invocation of a simulator application and view results as they occur.
To debug your design in Visualizer, you can either load results from a previous simulation (or emulation) or use a current (live) simulation. Once your application generates the design and waveform files, load them into Visualizer and start debugging your design.