Questa Verification IP
This course is for engineers who are verifying designs with standard protocols such as AMBA AXI, PCIe/NVMe, Ethernet, USB, serial, and many more, or designs with DRAM and Flash memories. Questa Verification IP (QVIP) supports these protocols and memories. QVIP comes with a library of protocol-specific sequences and testplans. QVIP can drive the bus and check responses with scoreboards and SystemVerilog Assertions. After completion of this course, engineers will be able to generate a UVM testbench with QVIP Configurator, and integrate QVIP into existing UVM testbenches. Hands-on lab exercises reinforce lecture and discussion topics under the guidance of our industry expert instructors.
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