Browse all Lessons in Siemens Verification Academy

January 2025

• Introduction to Functional Verification

  UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden Lesson

• Understanding the Two Main Testing Approaches

  UVM - Universal Verification Methodology Jan 10, 2025 Harry Foster Lesson

• What is a Reusable Testbench?

  UVM - Universal Verification Methodology Jan 10, 2025 Tom Fitzpatrick Lesson

• How Can I Reuse Testbench Components?

  UVM - Universal Verification Methodology Jan 10, 2025 Tom Fitzpatrick Lesson

• UVM Test Flow

  UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden Lesson

• Creating a Test Plan

  UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden Lesson

• Test Plan Fields

  UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden Lesson

• SystemVerilog Data Types

  UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden Lesson

• Multidimensional Arrays

  UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden Lesson

• Built-In Unpacked Arrays

  UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden Lesson

• Procedural Programming Statements

  UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden Lesson

• Introduction to Functional Coverage

  UVM - Universal Verification Methodology Jan 10, 2025 Harry Foster Lesson

• SystemVerilog Coverage Constructs

  UVM - Universal Verification Methodology Jan 10, 2025 Harry Foster Lesson

• Reusable Coverage, Reporting, and Options

  UVM - Universal Verification Methodology Jan 10, 2025 Harry Foster Lesson

• Sampling and Using Coverage

  UVM - Universal Verification Methodology Jan 10, 2025 Harry Foster Lesson

• Introduction to Constrained Random Stimulus

  UVM - Universal Verification Methodology Jan 10, 2025 Dave Rich Lesson

• Verilog Expression Impact on Constraints

  UVM - Universal Verification Methodology Jan 10, 2025 Dave Rich Lesson

• Issues Contributing to Randomization Failures

  UVM - Universal Verification Methodology Jan 10, 2025 Dave Rich Lesson

• Random Stimulus Probabilities and Statistics

  UVM - Universal Verification Methodology Jan 10, 2025 Dave Rich Lesson

• Random Variable and Constraint Features

  UVM - Universal Verification Methodology Jan 10, 2025 Dave Rich Lesson

• Connecting the DUT and Testbench

  UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden Lesson

• Interface Ports, Timing, and Direction

  UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden Lesson

• Implementing Protocol Signaling

  UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden Lesson

• Timing and Execution Semantics

  UVM - Universal Verification Methodology Jan 10, 2025 Harry Foster Lesson

• Threads

  UVM - Universal Verification Methodology Jan 10, 2025 Harry Foster Lesson