Five Signals from the 2026 Functional Verification Study

The forthcoming 2026 Siemens EDA and Wilson Research Group Functional Verification Study indicates that the IC verification problem is changing in nature, not simply growing in complexity. Declining first-silicon success, increased CPU/GPU/AI accelerator-class participation, near-universal reported embedded processor content across implementation categories, a broadening verification ecosystem, and greater visibility of firmware-, safety-, and security-related respin contributors all point toward a shift from verifying designs to building system confidence in software-driven silicon systems.

Introduction: Why this Study Feels Different

For most of the past 20 years, the Siemens EDA and Wilson Research Group Functional Verification Studies showed a difficult but familiar pattern. Designs became larger. Verification teams became more disciplined. Tools and methodologies improved. Verification planning matured, and advanced methods such as coverage-driven verification, assertions, formal verification, and emulation became more widely adopted.

The industry was not eliminating respins. But it appeared to be absorbing rising complexity well enough to keep first-silicon success within a relatively stable range. That stability mattered. It suggested that verification capability was rising with design complexity. The forthcoming 2026 Siemens EDA and Wilson Research Group Functional Verification Study¹ challenges that assumption.

In this context, this new operating state can be thought of as a new verification regime: one in which first-silicon success is no longer behaving within its historical range, and verification risk is increasingly shaped by system-level hardware/software interactions.

The issue is not simply that designs are more complex. Every generation of IC design has been more complex than the one before it. The more important question is whether the nature of verification risk has changed. A block can be correct. A protocol can be satisfied. Coverage can close. Formal properties can pass. Software can boot in emulation. Yet the final product can still fail when system-level interactions emerge under real operating conditions.

Those interactions often cut across architecture, firmware, workloads, power behavior, safety, security, and recovery. They may be validated separately, owned by different teams, or never stated explicitly until bring-up exposes them. That is why the 2026 study feels different. The study points to a shift: functional verification is no longer only about closing the design. It is increasingly about understanding the system before silicon becomes the first place where all interactions are fully revealed.

Reading the Signals Together

The 2026 study is most useful when the results are read as a pattern rather than as a set of isolated findings. No single datapoint explains the apparent decline in first-silicon success. Accelerator-class participation, embedded processor content, language adoption, and respin contributors can each be interpreted in more than one way. But when these measures move together, they point toward the same underlying theme: verification risk is becoming more system oriented.

That pattern matters because the hardest failures may no longer fit neatly into isolated RTL, firmware, safety, security, or methodology categories. They increasingly emerge at the boundaries between domains, where separately verified assumptions meet inside the integrated system.

The five signals that follow should therefore be read not as independent claims, but as connected evidence of a broader shift in functional verification.