Browse all content in Verification Academy: Articles, Cookbooks, Resources, Sessions, and Tracks

September 2026

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  Five Signals from the 2026 Functional Verification Study

  Planning, Measurement and Analysis Sep 08, 2026 Harry Foster Session

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  Five Signals from the 2026 Functional Verification Study

  Planning, Measurement and Analysis Sep 08, 2026 Harry Foster pdf

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  Five Signals from the 2026 Functional Verification Study

  Planning, Measurement and Analysis Sep 08, 2026 Harry Foster Paper

April 2025

• Faster Debug Using QuestaSim Interactive Coverage Analysis

  Simulation Apr 16, 2025 Justin Royse pdf

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  Faster Debug Using QuestaSim Interactive Coverage Analysis

  Simulation Apr 16, 2025 Justin Royse Webinar

January 2025

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  Connecting the Testbench to the Design

  UVM - Universal Verification Methodology Jan 10, 2025 Harry Foster Session

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  Interface Ports, Timing, and Direction

  UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden Lesson

• Interface Ports, Timing, and Direction

  UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden pdf

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  Implementing Protocol Signaling

  UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden Lesson

• Implementing Protocol Signaling

  UVM - Universal Verification Methodology Jan 10, 2025 Bob Oden pdf

May 2024

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  Optimizing Connectivity Verification Workflow with Python and Tcl Scripting

  Python May 07, 2024 Ariel Ansbacher Conference

March 2024

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  Tool Assisted Debug in Visualizer

  Debug Mar 01, 2024 Richa Jha - Siemens Eda Article

April 2021

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  Easy Test Writing with a Proxy-driven Testbench

  SystemVerilog Apr 06, 2021 Ray Salemi Webinar

March 2021

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  The Life of a SystemVerilog Variable

  SystemVerilog Mar 26, 2021 Dave Rich Webinar

• The Life of a SystemVerilog Variable

  SystemVerilog Mar 26, 2021 Dave Rich pdf

• The Life of a SystemVerilog Variable

  SystemVerilog Mar 26, 2021 Dave Rich pdf

March 2018

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  Interfaces and Virtual Interfaces

  UVM - Universal Verification Methodology Mar 15, 2018 Vm Team Chapter

September 2017

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  Visualizer: Livesim / Interactive

  Debug Sep 05, 2017 Tom Kiley Track

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  Driver and Receiving Tracing

  Debug Sep 05, 2017 Tom Kiley Demo

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  Adding Signals to the Wave Window

  Debug Sep 05, 2017 Tom Kiley Demo

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  Viewing Data Values

  Debug Sep 05, 2017 Tom Kiley Demo

March 2017

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  Artifacts of Custom Checkers in Questa Power Aware Dynamic Simulation

  Low Power Mar 01, 2017 Progyna Khondkar Article

March 2015

• Samsung: Clock-Domain Crossing Aware Sequential Clock Gating

  Clock-Domain Crossing Mar 15, 2015 Jianfeng Liu, Mi-Suk Hong, Kyungtae Do, Jung Yun Choi, Jaehong Park S. Lsi, Samsung Electronics Co. Ltd. pdf

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  Samsung: Clock-Domain Crossing Aware Sequential Clock Gating

  Clock-Domain Crossing Mar 15, 2015 Jianfeng Liu, Mi-Suk Hong, Kyungtae Do, Jung Yun Choi, Jaehong Park S. Lsi, Samsung Electronics Co. Ltd. Paper

October 2013

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  AMS Verification for High Reliability and Safety Critical Applications

  Analog Mixed-Signal Oct 01, 2013 Martin Vlach Article