Reset-Domain Crossing
The high-level complexities of modern System On Chip (SoC) designs have created a complex architecture of multiple asynchronous reset sources. It is imperative to ensure that the design is reset accurately under all modes of operation. Such complex reset interactions asserting at the transmitting flop may violate setup and hold time considerations in receiving flop in different asynchronous reset domain and cause metastable data at the output of receiving flop resulting in reset domain crossings.
A comprehensive and precise analysis is required to not only identify such crossings causing real and critical issues but also avoid reporting false bugs. This topic area focuses on advanced techniques to find reset-domain crossing errors in efficient way before they escape into silicon.
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Wednesday, May 22nd | 8:00 AM US/Pacific
Questa RDC Assist – Improving Designer Productivity and Enabling Faster RDC Verification Closure with Machine Learning
In this webinar, you will learn how RDC Assist helps users expedite their RDC Analysis and will discuss use models and best practices to utilize RDC Assist, and walk through a demo showing its power.
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Reset-Domain Crossing (RDC) Sessions
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New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
In this session, you will learn new RDC, methodology, and automation techniques including; how to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows, waiver management flows, creating custom synchronizers and considerations for low power designs with UPF. -
CDC and RDC Assist: Applying machine learning to accelerate CDC analysis
In this session, you will learn how the CDC and RDC Assist function of Questa CDC and Questa RDC use machine learning to accelerate setup, identification of design structures, and assist with constraint generation to help users achieve signoff more efficiently. -
Acceleration Without Compromise: How to Finish Faster with Hierarchical CDC+RDC Methodologies
In this session, you will learn how to properly deploy hierarchical methodologies in CDC and RDC verification such that neither accuracy nor the performance expected from a hierarchical flow is compromised. -
Questa Reset Domain Crossing (RDC)
This session will demonstrate the Questa RDC Verification Solution and will introduce key features in RDC GUI, like RDC Matrix, Directive Window and other debug features. -
RDC Overview & Questa RDC Methodology
In this session, you will learn more about Reset Domain Crossing problems and methods to address it. Then you will be introduced to the Questa-RDC solution, how it catches true RDC issues and what is our proposed methodology of RDC flow to filter noise and have better QoR. -
A Methodology for Comprehensive CDC+RDC Analysis
In this session, you will learn how to improve your comprehensive CDC and RDC methodology development schedules and predictability. -
Handling Reset Domain Crossing for Designs with Set-Reset Flops
This session specifically explores the different possible scenarios with such flops and problems introduced by these in the RDC closure. Which potentially can be dangerous and time consuming. -
Bringing Reset and Power Domains Together – Confronting UPF Instrumentation
This session specifically talks about the issues encountered in Reset Domain Crossing introduced by UPF instrumentation. UPF instrumentation may lead to higher number of new Resets which are not part of the design specification leading to huge verification turnaround time. -
Advance your Designs with Advances in CDC and RDC
In this session you will gain an understanding of valuable new capabilities available in Questa CDC, RDC and Signoff CDC. -
Confronting Inevitability: Finding Clock and Reset Issues Before They Find You
In this session, you will learn the full scope of synchronization issues and how Questa’s clock- and reset-domain crossing solution will help you avoid costly design flaws and accelerate your time to market. -
Why Reset Domain Crossing Verification is an Emerging Requirement
In this session, you will learn what RDC covers that CDC does not and the appropriate time in the development cycle to deploy RDC.
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Reset-Domain Crossing (RDC) Forum Discussion
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Concurrent Assertion :: To check the No. of Occurrence of ' ack ' within certain clocks
Jan 12, 2022 SystemVerilog -
Web Seminar Notification: Why Reset Domain Crossing Verification is an Emerging Requirement
Jul 03, 2019 Announcements
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Reset-Domain Crossing (RDC) Overview
Reset-Domain Crossing (RDC) Overview
Complex SoCs, like designs from automobile or aerospace industry, not only involve multiple clock domains, but even more complex reset architectures leading to many RDC domains. Resets are important part of any design as these lead a design to a known state. Designs involving functional safety may have many independent reset signals which may be used to reset selectively a part of the design, while rest of the design may be in the functional mode. This will lead to interactions between reset signals and data signals across reset domain boundaries. RDC signals can lead to functional issues and thus should be caught early in the design cycle.
The transmission of data across sequential elements that are reset by different asynchronous and soft reset domains can cause reset domain crossing (RDC) paths, which can lead to metastability. This metastability can cause unpredictable values to be propagated to down-stream logic and prevent a design from functioning normally. A proper reset domain crossing sign-off methodology is required to avoid metastability and other functional problems in chip designs.
Note that this meta-stability is different from the one which may occur due to clock domain crossing. So even if you have proper synchronization of a clock domain crossing between transmitter and receiver, it may still cause meta-stability due to asynchronous reset at transmitter which is in different reset domain from asynchronous reset at receiver.
RDC synchronizers are quite flexible and may not have standard structure like CDC Synchronizers of DMUX, FIFO and Handshake type. Simply timing the Reset assertion at transmitter side w.r.t. reset assertion at receiver is sufficient for isolating the RDC issue. Other ways are to block the Data transfer from Tx flop to Rx flop or clock path of the Receiver flop. All these checks are performed during RDC verification by the design team or the verification team.
Challenges and Considerations
Since the RDC synchronizers are flexible in nature, without any standard synchronizer structure, it becomes more crucial to ensure the design assumptions are correct through some advance technique in your RDC verification methodology for accurate and efficient analysis. This includes the protocol checking of design assumptions, better constraining or reducing the false reporting of RDCs.
Static verification tools often come with standard methodologies and goals for RDC verification. But improper constraints, assumptions and configurations in RDC analysis can lead to huge number of violations which are nothing but noise in the static analysis. For false violations verification engineers apply waivers. This adds to another burden of waiver management. It is often desired that the tools should have a methodology which has an automated data analysis or machine learning solution which can detect the issues in the setup and give corrective suggestions to verification engineers to eliminate noise.
Integrating RDC verification into the overall verification flow of a digital design poses challenges in terms of tool compatibility, data exchange, and coordination with other verification tasks such as functional verification and timing analysis. Addressing these challenges requires a combination of advanced verification techniques, comprehensive tool support, rigorous design practices, and domain expertise. By overcoming these challenges, designers can ensure the reliable operation of digital circuits, particularly in safety-critical applications where RDC issues can have severe consequences.
Reset-Domain Crossing (RDC) Conclusion
Reset-domain crossing (RDC) verification is no more a good to have kind of verification for designs with asynchronous resets, even if they are not high in number. There is a risk of Silicon failure due to meta-stability introduced for RDC, even if CDC verification is closed for the design, until you perform the RDC analysis. So RDC verification is a critical aspect of the digital design to ensure the reliable operation of the complex modern SoCs with asynchronous nature of reset signals.
A robust verification methodology is required for the exhaustive RDC analysis to catch the meta-stability issues early in the design cycle and mitigate the risks.
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