Related system verilog Constraint random verificatio

bharath123 · April 16, 2014, 7:22am

I wrote below as per requiement that i have various constrints depends randomized value on particular signal.

Iam not getting expected output having constraints like this.

For me requirement is : If(GOOD_PKT)
if(WR)
addr==4;
else if (RD)
addr==5;
else(BAD_PKT)
//tras type should be idle

This way i need to make constraints.

for me now always BAD_PKT is getting generated and trans type is idle.
If you have any questions ask me on code.
/////////////////////////////////////////////////////////////////////////////////////
program classex;
class pkt_ex;
typedef enum {BAD_PKT,GOOD_PKT} pkt_type_e;
typedef enum {RD,WR,IDLE} trans_type_e;
rand pkt_type_e pkt_type;
rand trans_type_e trans_type;
rand bit [7:0] addr;

constraint trans_bpc {(pkt_type==BAD_PKT)-> trans_type==IDLE;}
constraint addr_idlec {(trans_type==IDLE) → addr==4; }
constraint trans_gpc {(pkt_type==GOOD_PKT)-> trans_type==(RD || WR);}
constraint addr_rdc {(trans_type==RD) → addr==5; }
constraint addr_wrc {(trans_type==WR) → addr==6; }
endclass

initial begin
pkt_ex pkt_inst;
pkt_inst=new();

for(int i=0; i<5; i++) begin
 $display($time,"Inside repeat"); 
 pkt_inst.randomize();
end
 #2;

$display("%s %s %h \n",pkt_inst.pkt_type,pkt_inst.trans_type,pkt_inst.addr);

end
endprogram
///////////////////////////////////////////////////////////////////////////////////////////////

Thanks
Bharath

cgales · April 16, 2014, 12:12pm

In your example, you are randomizing 5 times but only $display(ing) the last one. Since your pkt_type has a 50% chance of being bad, it’s possible that you will only $display a BAD_PKT. Additionally, if you simulate with the same random seed, you will always get the same result due to random stability.

If you $display each randomization result and run with different seeds, you should see a 50/50 mix of BAD_PKT and GOOD_PKT.

bharath123 · April 16, 2014, 5:03pm

In reply to cgales:

I have update in code and modified the condtraints still iam getting result as PKT_TYPE=BAD_TYPE,trans_type=IDLE.

Output is:

vsim -sv_seed random classex_opr

Loading sv_std.std

Loading work.classex_opr(fast)

Sv_Seed = 108451649

run

Hello: pkt_type_0 = 1 ,trans_type_0 = 2 pkt_type = BAD_PKT ,trans_type = IDLE addr= 6

1 Simulation stop requested

Code:

program classex_opr;
typedef enum {GOOD_PKT,BAD_PKT} pkt_type_e;
typedef enum {WR,RD,IDLE} trans_type_e;
class pkt_cons;
randc pkt_type_e pkt_type;
randc trans_type_e trans_type;
rand bit [7:0] addr;

constraint pkt_type_gdwc {(pkt_type==GOOD_PKT)-> trans_type== WR;}

constraint pkt_type_gdrd {(pkt_type==GOOD_PKT)-> trans_type== RD;}
constraint pkt_type_bdidle{(pkt_type==BAD_PKT)-> trans_type== IDLE;}
constraint trans_type_wrc {(trans_type==WR)-> addr==4;}
constraint trans_type_rdc{(trans_type==RD)-> addr==5;}
constraint trans_type_idlec {(trans_type==IDLE)-> addr==6;}

endclass

initial begin
pkt_cons pkt1_inst;
pkt1_inst=new();
for(int i= 0; i<10;i++) begin
pkt1_inst.randomize();

$display("Hello: pkt_type_0 = %d ,trans_type_0 = %d pkt_type = %s ,trans_type = %s addr=%d",pkt1_inst.pkt_type,pkt1_inst.trans_type,pkt1_inst.pkt_type,pkt1_inst.trans_type,pkt1_inst.addr);

end
end
endprogram

Naven8 · April 16, 2014, 5:35pm

In reply to bharath123:

The above code has some problem. for the same packet type you are defining two transaction types. Constraint solver will fail.

constraint pkt_type_gdwc {(pkt_type==GOOD_PKT)-> trans_type== WR;}
constraint pkt_type_gdrd {(pkt_type==GOOD_PKT)-> trans_type== RD;}

Naven8 · April 16, 2014, 5:45pm

In reply to aming:

Just with little changes i am getting proper seq.

program classex_opr;
typedef enum {GOOD_PKT,BAD_PKT} pkt_type_e;
typedef enum {WR,RD,IDLE} trans_type_e;
class pkt_cons;
randc pkt_type_e pkt_type;
rand trans_type_e trans_type;
rand bit [7:0] addr;

constraint pkt_type_gdwc {(pkt_type==GOOD_PKT)-> trans_type inside {WR, RD};}
//constraint pkt_type_gdrd {(pkt_type==GOOD_PKT)-> trans_type== RD;}
constraint pkt_type_bdidle{(pkt_type==BAD_PKT)-> trans_type== IDLE;}
constraint trans_type_wrc {(trans_type==WR)-> addr==4;}
constraint trans_type_rdc{(trans_type==RD)-> addr==5;}
constraint trans_type_idlec {(trans_type==IDLE)-> addr==6;}

endclass


initial begin
pkt_cons pkt1_inst;
pkt1_inst=new();
for(int i= 0; i<10;i++) begin
pkt1_inst.randomize();

$display("Hello: pkt_type_0 = %d ,trans_type_0 = %d pkt_type = %s ,trans_type = %s addr=%d",pkt1_inst.pkt_type,pkt1_inst.trans_type,pkt1_inst.pkt_type,pkt1_inst.trans_type,pkt1_inst.addr);
end
end
endprogram

HHello: pkt_type_0 = 1 ,trans_type_0 = 2 pkt_type = BAD_PKT ,trans_type = IDLE addr= 6
Hello: pkt_type_0 = 0 ,trans_type_0 = 0 pkt_type = GOOD_PKT ,trans_type = WR addr= 4
Hello: pkt_type_0 = 0 ,trans_type_0 = 0 pkt_type = GOOD_PKT ,trans_type = WR addr= 4
Hello: pkt_type_0 = 1 ,trans_type_0 = 2 pkt_type = BAD_PKT ,trans_type = IDLE addr= 6
Hello: pkt_type_0 = 1 ,trans_type_0 = 2 pkt_type = BAD_PKT ,trans_type = IDLE addr= 6
Hello: pkt_type_0 = 0 ,trans_type_0 = 0 pkt_type = GOOD_PKT ,trans_type = WR addr= 4
Hello: pkt_type_0 = 0 ,trans_type_0 = 1 pkt_type = GOOD_PKT ,trans_type = RD addr= 5
Hello: pkt_type_0 = 1 ,trans_type_0 = 2 pkt_type = BAD_PKT ,trans_type = IDLE addr= 6
Hello: pkt_type_0 = 0 ,trans_type_0 = 1 pkt_type = GOOD_PKT ,trans_type = RD addr= 5
Hello: pkt_type_0 = 1 ,trans_type_0 = 2 pkt_type = BAD_PKT ,trans_type = IDLE addr= 6

cgales · April 16, 2014, 6:05pm

In reply to Naven8:

You should note that randomize() is a function call with a return code that tells you if it is successful or not.

Your code should look something like:


if (!pkt1_inst.randomize()) $display("Randomize error!");
else $display("Hello: pkt_type_0 = %d ,trans_type_0 = %d pkt_type = %s ,trans_type = %s addr=%d",pkt1_inst.pkt_type,pkt1_inst.trans_type,pkt1_inst.pkt_type,pkt1_inst.trans_type,pkt1_inst.addr);

VE1 · April 16, 2014, 6:20pm

In reply to Naven8:

bharath123 :
please try ::
constraint pkt_type_gdwc {(pkt_type==GOOD_PKT)-> trans_type inside {RD,WR};}
For details of this issue you may refer to Dave comment
Assertion error, why? | Verification Academy