Related system verilog Constraint random verificatio

bharath123 · April 16, 2014, 5:03pm

In reply to cgales:

I have update in code and modified the condtraints still iam getting result as PKT_TYPE=BAD_TYPE,trans_type=IDLE.

Output is:

vsim -sv_seed random classex_opr

Loading sv_std.std

Loading work.classex_opr(fast)

Sv_Seed = 108451649

run

Hello: pkt_type_0 = 1 ,trans_type_0 = 2 pkt_type = BAD_PKT ,trans_type = IDLE addr= 6

1 Simulation stop requested

Code:

program classex_opr;
typedef enum {GOOD_PKT,BAD_PKT} pkt_type_e;
typedef enum {WR,RD,IDLE} trans_type_e;
class pkt_cons;
randc pkt_type_e pkt_type;
randc trans_type_e trans_type;
rand bit [7:0] addr;

constraint pkt_type_gdwc {(pkt_type==GOOD_PKT)-> trans_type== WR;}

constraint pkt_type_gdrd {(pkt_type==GOOD_PKT)-> trans_type== RD;}
constraint pkt_type_bdidle{(pkt_type==BAD_PKT)-> trans_type== IDLE;}
constraint trans_type_wrc {(trans_type==WR)-> addr==4;}
constraint trans_type_rdc{(trans_type==RD)-> addr==5;}
constraint trans_type_idlec {(trans_type==IDLE)-> addr==6;}

endclass

initial begin
pkt_cons pkt1_inst;
pkt1_inst=new();
for(int i= 0; i<10;i++) begin
pkt1_inst.randomize();

$display("Hello: pkt_type_0 = %d ,trans_type_0 = %d pkt_type = %s ,trans_type = %s addr=%d",pkt1_inst.pkt_type,pkt1_inst.trans_type,pkt1_inst.pkt_type,pkt1_inst.trans_type,pkt1_inst.addr);

end
end
endprogram