Related system verilog Constraint random verificatio

SystemVerilog
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In reply to bharath123:

The above code has some problem. for the same packet type you are defining two transaction types. Constraint solver will fail.

constraint pkt_type_gdwc {(pkt_type==GOOD_PKT)-> trans_type== WR;}
constraint pkt_type_gdrd {(pkt_type==GOOD_PKT)-> trans_type== RD;}