Verification Academy

Topic	Replies	Views	Activity
Welcome to our Verification Academy community! Announcements	1	556	September 13, 2023
Cross coverage of coverpoints sampling on different addresses SystemVerilog SystemVerilog , Coverage , cross-coverage	2	10	March 26, 2025
Need suggestions for fork join_any SystemVerilog argument-pass-by-ref	18	88	March 26, 2025
Timescale versus UVM info? UVM UVM , realtime , Timescale	3	11	March 26, 2025
What happens if I pass argument in item done() and if I did not pass also what happens? UVM UVM	0	6	March 26, 2025
Need to get a constraint with in the 2KB boundary SystemVerilog SystemVerilog	2	27	March 26, 2025
How to verify the reliability of a VIP before integration? UVM VIP-integration , VIP	1	10	March 26, 2025
Using a function in a virtual class to determine a parameter SystemVerilog SystemVerilog , Virtual-class , constant-function	1	12	March 25, 2025
Need to get the repeated value in an array how many times it got repeated and the first index where the repeated value is SystemVerilog SystemVerilog	3	26	March 25, 2025
Create a coverpoint to sample non default value SystemVerilog Coverage , coverpoint	1	15	March 25, 2025
Streaming operator SystemVerilog	4	26	March 25, 2025
Constraint to generate pattern SystemVerilog SystemVerilog	4	15	March 25, 2025
What is uvm_reg.has_reset(.delete(1))? UVM UVM	0	14	March 25, 2025
UVM RAL model for register and memory with overlapping address and accessing them using the same interface UVM RAL , RAL-register-UVM , uvm-ral	3	46	March 24, 2025
Loops inside property block SystemVerilog SystemVerilog , assertion , SVA , Assertion-property	1	17	March 24, 2025
Incremental compilation or partition compilation SystemVerilog	1	27	March 24, 2025
Adding uvm callback in derived environment UVM UVM-callback	2	23	March 24, 2025
I cannot find any implementations of a class that extends uvm_reg_file UVM SystemVerilog , UVM , RAL , System-Verilog , uvm-ral , uvm_ral , uvm_reg_file , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , register-file , register-model-structure	1	25	March 23, 2025
Interview Questions on Assertions SystemVerilog SystemVerilog , UVM	23	19698	March 22, 2025
How to retrieve the correct values of continuously driven values of DUT in the test bench SystemVerilog	0	15	March 22, 2025
Boundaries of $past(d) and current value of d for verifying D flip flop SystemVerilog assertion	3	44	March 21, 2025
Why does using a generic interface port (without modports) allow both dut0 and dut1 to drive data and enable without error, while using modports enforces directionality and prevents such assignments? SystemVerilog systemverilog-interface	0	17	March 21, 2025
SVA - use different clocks in the property from the sample clock SystemVerilog SVA	3	31	March 20, 2025
Uvm virtual sequence UVM UVM	11	1204	March 20, 2025
Using `uvm_error before start_of_simulation UVM uvm_phases	4	33	March 19, 2025
How to debug : never ending uvm_do UVM	1	25	March 19, 2025
Need to get the ending address for 180 bytes of data transfer if the starting address is FFF0 and need to consider the AXI 4KB boundary. Bus width is 64 bit SystemVerilog	0	20	March 19, 2025
Binding a module to another module's modport interface SystemVerilog assertion , SVA , Assertion-Based-Verification , SVA-Assertion , assertion-systemverilog , Assertion-system-verilog	10	77	March 17, 2025
SV bind and Part compilation SystemVerilog	3	37	March 18, 2025
Develop 5 threads by using threads concept and make sure if any of 3 threads are completed out of 5 threads then kill other 2 threads SystemVerilog SystemVerilog , thread , for-loop-fork-join_none , fork-join_any , fork , disable-fork , fork-join , fork_join , threads , thread-fork	5	46	March 18, 2025

Welcome to our Verification Academy community!

Announcements

1

556

September 13, 2023

Cross coverage of coverpoints sampling on different addresses

SystemVerilog

SystemVerilog , Coverage , cross-coverage

2

10

March 26, 2025

Need suggestions for fork join_any

SystemVerilog

argument-pass-by-ref

18

88

March 26, 2025

Timescale versus UVM info?

UVM

UVM , realtime , Timescale

3

11

March 26, 2025

What happens if I pass argument in item done() and if I did not pass also what happens?

UVM

0

6

March 26, 2025

Need to get a constraint with in the 2KB boundary

SystemVerilog

2

27

March 26, 2025

How to verify the reliability of a VIP before integration?

UVM

VIP-integration , VIP

1

10

March 26, 2025

Using a function in a virtual class to determine a parameter

SystemVerilog

SystemVerilog , Virtual-class , constant-function

1

12

March 25, 2025

Need to get the repeated value in an array how many times it got repeated and the first index where the repeated value is

SystemVerilog

3

26

March 25, 2025

Create a coverpoint to sample non default value

SystemVerilog

Coverage , coverpoint

1

15

March 25, 2025

Streaming operator

SystemVerilog

4

26

March 25, 2025

Constraint to generate pattern

SystemVerilog

4

15

March 25, 2025

What is uvm_reg.has_reset(.delete(1))?

UVM

0

14

March 25, 2025

UVM RAL model for register and memory with overlapping address and accessing them using the same interface

UVM

RAL , RAL-register-UVM , uvm-ral

3

46

March 24, 2025

Loops inside property block

SystemVerilog

SystemVerilog , assertion , SVA , Assertion-property

1

17

March 24, 2025

Incremental compilation or partition compilation

SystemVerilog

1

27

March 24, 2025

Adding uvm callback in derived environment

UVM

UVM-callback

2

23

March 24, 2025

I cannot find any implementations of a class that extends uvm_reg_file

UVM

SystemVerilog , UVM , RAL , System-Verilog , uvm-ral , uvm_ral , uvm_reg_file , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , register-file , register-model-structure