Verification Academy

Topic	Replies	Views	Activity
Welcome to our Verification Academy community! Announcements	0	798	December 27, 2022
Detection of Interrupt in Monitor UVM UVM , virtual-interface , rose	7	150	August 28, 2026
Non integral expressions SystemVerilog SystemVerilog	7	2098	August 26, 2026
Valid expression types in the with clause SystemVerilog SystemVerilog , array-reduction-methods , with-clause	4	49	August 26, 2026
Lifespan of memory of objects created during run_phase UVM UVM , UVM-MEMORY-MODELING , uvm_object	0	17	August 26, 2026
Unexpected Behaviour From Xilinx Vivado? SystemVerilog SystemVerilog	1	23	August 24, 2026
Class :final TopPacket extends LinkedPacket; SystemVerilog SystemVerilog	4	59	August 18, 2026
How to generate wlf using qrun command SystemVerilog	1	39	August 17, 2026
What happen if the antecedent occurs or it is true, but the consequent will never occur? SystemVerilog SVA	6	78	August 16, 2026
Preparing test plan for SPI protocol in UVM UVM UVM , SPI , SPI-protocol , SPI-Test-Plan , UVM-SPI-testbench	5	3305	August 13, 2026
Debugging VIP's API calls SystemVerilog SystemVerilog , Polymorphism	1	80	August 3, 2026
Merits of Overriding Sequence Items UVM UVM , Cookbook-SequencesOverrides	3	766	August 3, 2026
Sva and ai with rag rules SystemVerilog	1	108	July 27, 2026
Question on UVM Phases UVM UVM , UVM-phases , uvm_phases	1	125	July 24, 2026
What is the difference between uvm_config_db and uvm_resource_db? UVM UVM , uvm_config	22	43773	July 21, 2026
Type v/s Size cast within with clause of sum() SystemVerilog SystemVerilog , constraint-randomization , array-reduction-methods	5	141	July 15, 2026
is $fell(sig_a) true when sig_a from x to 0? SystemVerilog assertion , SVA	4	208	July 13, 2026
The question of disable SystemVerilog	6	93	July 13, 2026
Why create method is not part of uvm_object_wrapper? UVM uvm-factory	3	128	July 10, 2026
Resulting sign and bit length using Conditional Operator SystemVerilog SystemVerilog , Conditional-Operator , Ternary-Operator	4	104	July 9, 2026
DisplayPort Protocol (version 1.4) UVM Spec-Clarification	0	88	July 7, 2026
The difference between a looped `fork...join_none` and a serial `fork...join_none` SystemVerilog	5	111	July 7, 2026
Questions about the usage of Pattern Matching Conditional Statements SystemVerilog	3	85	July 6, 2026
How do we integrate the toolchain with uvm? UVM SystemVerilog , UVM	1	83	July 2, 2026
Determining the bit width of operands in constraint SystemVerilog constraint-randomization , Evaluating-a-Constraint-expression , Size-Cast , Constraint-Expression	4	110	July 1, 2026
Assignment rules for different width & sign SystemVerilog SystemVerilog , signed , casting , assignment	5	86	July 1, 2026
What are the biggest pain points in simulation debugging for DV engineers? UVM SystemVerilog	2	108	July 1, 2026
Monitor-to-Scoreboard Connection UVM UVM	3	185	July 1, 2026
Difference between put_port and get_port? UVM UVM , put_port	8	2527	June 30, 2026
Why are UVM User-Defined Phase Classes Implemented as Singletons? UVM UVM	1	94	June 29, 2026