Verification Academy

Topic	Replies	Views	Activity
Welcome to our Verification Academy community! Announcements	1	751	September 13, 2023
TIC TAC TOE Snapshot generation using SystemVerilog constraints SystemVerilog SystemVerilog	9	5443	March 30, 2026
Asynchronous_FIFO Design SystemVerilog SystemVerilog	0	2	March 30, 2026
Question regarding the generate block SystemVerilog SystemVerilog	2	3	March 30, 2026
User-defined verbosity using uvm_config_db UVM	1	12	March 30, 2026
Regarding stress test cases SystemVerilog	1	15	March 30, 2026
Question regarding the scheduling order after an event is triggered SystemVerilog SystemVerilog	2	21	March 27, 2026
Using @* with forever block in testbench code SystemVerilog	2	42	March 23, 2026
Choosing between TLM get v/s peek UVM tlm , uvm_blocking_peek_imp , uvm_blocking_get_imp , get-vs-peek	1	36	March 22, 2026
ref argument default value SystemVerilog SystemVerilog	1	27	March 19, 2026
Execution of function after it unblocks SystemVerilog uvm_analysis_imp , analysis-port , uvm_analysis_imp_decl , function-as-task , blocking-function	1	41	March 17, 2026
SVA on intersect SystemVerilog assertion	6	93	March 17, 2026
Soft constraints must be followed by an expression SystemVerilog constraint-randomization , soft-constraints , Implication-constraint	7	65	March 16, 2026
Constraint for a prime number SystemVerilog SystemVerilog , prime-number-constraint , systemverilog-constraint	3	1288	March 16, 2026
Bug (?) in uvm_pool UVM SystemVerilog , UVM , uvm_event_pool	0	33	March 13, 2026
Back door access for uvm_mem UVM UVM	3	1442	March 13, 2026
Race Between Assign and multiple Initial Blocks SystemVerilog	2	47	March 13, 2026
Randomization of req signal in priority arbiter SystemVerilog constraint-randomization , Priority-arbiter	7	136	March 11, 2026
UVM Verification of I2C Slave IP with APB Registers UVM UVM , Coverage , System-Verilog , SVA	2	54	March 10, 2026
Race between procedural Blocks and always block triggering itself SystemVerilog	2	30	March 8, 2026
assertion to detect a specific switch of a signal SystemVerilog assertion	3	50	March 6, 2026
Upward references in bound interfaces SystemVerilog	5	59	March 3, 2026
Ensuring specific uvm_config_db::set always wins UVM UVM , uvm_config_db	0	67	February 24, 2026
Iteration of elements in an array declared as randc SystemVerilog randc	2	58	February 24, 2026
Configuring agent in Active / Passive mode UVM uvm_config_db , activepassive-agent-configuration , uvm_agent , uvm_active_passive_enum	5	141	February 22, 2026
Bind interface for internal DUT forcing UVM UVM	20	5518	February 21, 2026
Default argument dimension & type in SV subroutines SystemVerilog subroutine , SV-Function , SV-Subroutines	1	29	February 21, 2026
SV Assertions practice questions SystemVerilog assertion	0	75	February 21, 2026
Assertion failure using strong property SystemVerilog SVA , Sva-strong , strong-property , fail-action-block	7	84	February 19, 2026
Automation of creating different parameter sets combinations UVM IP-Parameter	1	40	February 18, 2026