Verification Academy

Topic	Replies	Views	Activity
Welcome to our Verification Academy community! Announcements	1	331	September 13, 2023
My Driver, Monitor & Scoreboard run at 0 Semulation time... Whats the problam UVM UVM	2	4	July 27, 2024
How to add this feathuer to genrate my scan_en signal pulse is high fo 2 clock pulse and then low rest of the clock pulse UVM SystemVerilog , constraint-randomization	0	2	July 27, 2024
Drv.seq_item_port.connect(seqr.seq_item_export); UVM	1	3	July 27, 2024
How to verify the internal state in uvm UVM riscv-uvm	1	7	July 27, 2024
Correct way to kill sequences UVM UVM , stop_seqeunces	9	6723	July 26, 2024
Uvm_path_e vs uvm_door_e UVM SystemVerilog , UVM , uvm-ral	2	8	July 26, 2024
Sequence Stop or Kill UVM SystemVerilog , UVM	2	16	July 26, 2024
Phase raise and drop objection UVM SystemVerilog , UVM	4	22	July 26, 2024
Assertion for signal toggling SystemVerilog assertion	4	33	July 26, 2024
Suggestions for uvm_phase API UVM UVM , UVM_PHASE	1	15	July 25, 2024
Constraint to generate a pattern SystemVerilog SystemVerilog , constraint-randomization	13	242	July 25, 2024
Using the string I provided in the create function UVM SystemVerilog , UVM	2	18	July 25, 2024
How to pass a value from UVM to tb_top - value used to set virtual interfaces UVM	3	19	July 24, 2024
What are the various approaches for verifying a design that contain an ARM processor like A9,A72,R5 etc in UVM? UVM SOC-verification , processor-verification , FPGA-Verification , Top-level-verification , Chip-level-verification , ASIC-Verification	0	17	July 24, 2024
Analysis Export and Fifo in an uvm_object? UVM UVM , uvm_object , uvm_tlm_analysis_fifo , analysis-export	7	1813	July 24, 2024
Override by type with name conflicts UVM UVM , factory , set_type_override_by_type , factory-overrides , uvm-factory , uvm-factory-override	1	50	July 24, 2024
Arithmetic with signed numbers SystemVerilog SystemVerilog	3	46	July 23, 2024
What is the difference between uvm_config_db and uvm_resource_db? UVM UVM , uvm_config	17	41757	July 23, 2024
Why is it invalid to connect a single blocking_put_port to multiple imps? UVM UVM	2	27	July 23, 2024
Why UVM allows connecting multiple exports/imps to a single put port UVM UVM , export-and-port , UVM-TLM-Port_Export	1	457	July 23, 2024
Declaration of a Default Value on 2 Dimensional Array SystemVerilog	1	26	July 23, 2024
Asynchronous reset and clocking block SystemVerilog SystemVerilog	1	949	July 23, 2024
Instance of agent in other agent SystemVerilog SystemVerilog	1	32	July 22, 2024
Constraints on dynamic array SystemVerilog SystemVerilog , dynamicarray-constraint	6	826	July 22, 2024
Nested functions compile warning SystemVerilog	1	27	July 22, 2024
Coverage class - how to best pass in the variable being covered Coverage UVM-Coverage	1	29	July 22, 2024
Uvm_event ordering UVM SystemVerilog , UVM	1	37	July 21, 2024
SystemVerilog Clocking Block Timing Behavior with cycle delays - Need Clarification SystemVerilog SystemVerilog	2	41	July 20, 2024
Entering unknown number of real numbers SystemVerilog	1	24	July 20, 2024