Verification Academy

Topic	Replies	Views	Activity
Welcome to our Verification Academy community! Announcements	1	467	September 13, 2023
Constraint Randomization Interview Question SystemVerilog SystemVerilog	20	4807	November 21, 2024
Write constraint for an integer array with 10 elements such that exactly 3 of them are same and rest are unique SystemVerilog SystemVerilog , unique-array	9	2116	November 20, 2024
Toggle Coverage for a 8bit variable UVM functional-coverage	1	22	November 20, 2024
How using Functional Coverage we can find out, if there is any missing functionality in the DUT? SystemVerilog SystemVerilog	4	839	November 20, 2024
Factory in RAL , create vs new UVM RAL	1	19	November 19, 2024
SV Constraint with Permutations and Combinations SystemVerilog	2	29	November 19, 2024
Mirrored value in frontdoor and backdoor UVM RAL	1	15	November 19, 2024
Constraining OCM base addresses SystemVerilog SystemVerilog , constraint-randomization	1	14	November 19, 2024
Write a constraint to generate the pattern 1234554321 SystemVerilog SystemVerilog , systemverilog-constraint	1	21	November 19, 2024
Constrain block to allocate dedicated non over-lapping address range space for 16 masters SystemVerilog SystemVerilog , systemverilog-randomization	7	1789	November 19, 2024
Adding a function in constraint doesn't work UVM constraint , constraint-randomization	2	24	November 18, 2024
Question on Fork join with case statement SystemVerilog SystemVerilog , fork-join	3	38	November 18, 2024
Bit Constraints of each element in array SystemVerilog constraints	5	35	November 18, 2024
One register map for multiple agents? CONTINUED UVM	4	47	November 18, 2024
Array vs queue SystemVerilog SystemVerilog	3	1234	June 23, 2015
Coverage in Monitor UVM UVM	2	24	November 17, 2024
Coverpoint for a bit transition Coverage Transition-Coverage	1	34	November 15, 2024
Best practice to align interfaces in UVM testbench UVM UVM	6	46	November 14, 2024
Variable delay in SV SystemVerilog	3	34	November 14, 2024
Calling of build phase? UVM UVM , UVM_PHASE , build_phase	26	19928	November 14, 2024
Downcasting extended class and base class SystemVerilog	3	34	November 14, 2024
Difference between get_next_item and get? UVM UVM	8	5335	November 14, 2024
Properly Constraining Signed Logic Dynamic Array SystemVerilog	6	45	November 13, 2024
Is there a dummy simulation that I could use to compare runtime of different machines SystemVerilog	5	40	November 13, 2024
Mutiple monitor single scoreboard UVM	0	40	November 12, 2024
Assertion having multiple clocks SystemVerilog assertion	1	47	November 12, 2024
Synchronization using event and mailbox SystemVerilog	3	36	November 12, 2024
Forcing values of bind ports through concatenated signals on inner instance port connection SystemVerilog bind , force-signal	6	19	November 12, 2024
After removing get_response () I am not seeing the second transaction initiated by master UVM UVM	7	46	November 12, 2024