Verification Academy

Topic	Replies	Views	Activity
Welcome to our Verification Academy community! Announcements	1	220	September 13, 2023
Using sequence method triggered within Sampled value functions SystemVerilog SystemVerilog , assertion , SVA , SVA-Assertion	4	40	April 27, 2024
How text macro affect inside and outside pkg? SystemVerilog SystemVerilog , compilation-macro	2	7	April 27, 2024
Example of Constructors from LRM SystemVerilog	3	18	April 26, 2024
How do you compare negative integers in systemVerilog? SystemVerilog	5	27	April 26, 2024
How to know about which seed is running and getting randomize when my seed is processed randomly? Coverage Coverage , SEED , code-coverage , run_test4-clean-lib-cmp-vsim-VSIMBATCH4-coverage-vopt-sva-sv_seed-random	5	352	April 26, 2024
Clarifications about uvm_config db performance UVM	3	28	April 26, 2024
For below Assert property i'm getting offending error, can anyone help me with this SystemVerilog assertion	7	56	April 26, 2024
How to set the config_db multiple times? UVM UVM	8	4677	April 26, 2024
Can we use tlm ports if so many componemts are there in sequence ordered defined like UVM	3	18	April 25, 2024
What could be the reason for infinite loop in our code when dealing with sequence and driver UVM	1	25	April 24, 2024
How to kill fork join if some of the threads ae finished SystemVerilog	1	25	April 25, 2024
Register mirrored value should update until an event happens in temporal domain UVM	1	14	April 25, 2024
Passing queue of structs by ref SystemVerilog	2	20	April 24, 2024
Performance problem SystemVerilog SystemVerilog	3	51	April 24, 2024
Whether to use TLM ports or class object set in the uvm_config_db UVM	4	26	April 24, 2024
Constraint Randomization Interview Question SystemVerilog SystemVerilog	17	4262	April 24, 2024
Vopt-13412) Virtual methods of an object or built-in method are not allowed in event control expressions SystemVerilog SystemVerilog	1	23	April 23, 2024
Hierarchical uvm_reg_block add hdl path UVM	0	16	April 24, 2024
Arr.sum() - constraint SystemVerilog SystemVerilog , systemverilog-constraint	1	39	April 23, 2024
Basic rule to use assertion in UVM UVM assertion	1	31	April 23, 2024
Calling a function with class argument inside a constraint SystemVerilog	2	25	April 23, 2024
What is the general difference between static and dynamic events in SystemVerilog? SystemVerilog SystemVerilog	3	905	April 23, 2024
N Queen Board Problem in SV Constraint SystemVerilog SystemVerilog , systemverilog-constraint , array-reducation , Constraint-Interview-Question	7	579	April 23, 2024
Skipping a register field from comparison with RAL UVM RAL , uvm_ral , RAL-UVM	5	40	April 23, 2024
How to pass delay through a variable in assertion SystemVerilog SystemVerilog	7	1999	April 23, 2024
Constraint for walking pattern (walking 1's) SystemVerilog systemverilog-constraint , uvm-sv-constraints	7	118	April 19, 2024
Uvm_hdl_read using macro for string path UVM	1	20	April 22, 2024
If virtual sequencer contain a source sequencer and and destination sequencer and in test I am calling seq.start(envh.v_seqrh) then how ill the tool know to start the sequences on source sequencer or destination sequencer UVM	2	35	April 22, 2024
Write a constraint that assigns data to any address sequence that follows an arithmetic progression (ex: 1,5,9,13,17.. so a[1]=30, a[5]=30, a[9]=30 and so on)) SystemVerilog constraint , constraint-randomization , systemverilog-constraint	5	53	April 21, 2024