Verification Academy

Topic	Replies	Views	Activity
Welcome to our Verification Academy community! Announcements	1	775	September 13, 2023
Questions about the usage of Pattern Matching Conditional Statements SystemVerilog	0	8	July 3, 2026
How do we integrate the toolchain with uvm? UVM SystemVerilog , UVM	1	28	July 2, 2026
Type v/s Size cast within with clause of sum() SystemVerilog SystemVerilog , constraint-randomization , array-reduction-methods	1	18	July 1, 2026
Determining the bit width of operands in constraint SystemVerilog constraint-randomization , Evaluating-a-Constraint-expression , Size-Cast , Constraint-Expression	4	40	July 1, 2026
Assignment rules for different width & sign SystemVerilog SystemVerilog , signed , casting , assignment	5	24	July 1, 2026
What are the biggest pain points in simulation debugging for DV engineers? UVM SystemVerilog	2	32	July 1, 2026
Monitor-to-Scoreboard Connection UVM UVM	3	32	July 1, 2026
Difference between put_port and get_port? UVM UVM , put_port	8	2468	June 30, 2026
Why are UVM User-Defined Phase Classes Implemented as Singletons? UVM UVM	1	26	June 29, 2026
[SVA Question] Signal 'b' has to toggle only once within 10cycle window of signal 'a' after 'a' is asserted SystemVerilog assertion , SVA , SVA-Assertion	7	137	June 28, 2026
Unclear scheduling semantics for a flip-flop model with assign/deassign SystemVerilog SystemVerilog	4	30	June 27, 2026
Doing some academic research on AI for chip design. Would anyone be willing to share their experience. SystemVerilog	1	32	June 26, 2026
Clarification regarding task run_phase() in UVM UVM	1	21	June 26, 2026
implement a reference counter UVM UVM	3	38	June 25, 2026
Where to implement memory read/write operations in UVM agent when observing packet transactions in monitor? UVM UVM	3	56	June 23, 2026
Using uvm field automation macros in uvm_object extended types UVM UVM , uvm_config_db , field-macros	3	31	June 23, 2026
Terminology related to the formal tool SystemVerilog assertion	0	24	June 23, 2026
Understanding Array Reduction methods SystemVerilog constraint-arraysum , array-reduction-methods	10	111	June 18, 2026
QCX not activating with optimized UVM testbench (qsim only, no qopt -qcx license) Coverage UVM , Coverage	2	20	June 17, 2026
Using uvm_config_db::get(null, ...) Inside a UVM Sequence (uvm_object) UVM UVM	2	45	June 15, 2026
Uvm_config_db set in the below example correct? UVM	1	108	June 15, 2026
UVM Field Macros - Positive flag UVM	1	30	June 15, 2026
Layered Protocol Response Mechanism UVM get_response	0	36	June 15, 2026
Assertion not triggering for Asynchronous FIFO SystemVerilog assertion	1	35	June 15, 2026
Constraint 2d array using SUM operator SystemVerilog SystemVerilog , constraint	0	54	June 15, 2026
UVM Driver Communication: get_next_item()/item_done() vs get()/put() — Which is Preferred in Industry? UVM UVM	5	66	June 14, 2026
Constraint for memories SystemVerilog SystemVerilog , constraints	9	6595	June 13, 2026
Random Non overlapping Address (Memory allocator) SystemVerilog SystemVerilog	3	6450	June 13, 2026
Return value of pack() and unpack() UVM	1	32	June 12, 2026

Welcome to our Verification Academy community!

Announcements

1

775

September 13, 2023

Questions about the usage of Pattern Matching Conditional Statements

SystemVerilog

0

8

July 3, 2026

How do we integrate the toolchain with uvm?

UVM

SystemVerilog , UVM

1

28

July 2, 2026

Type v/s Size cast within with clause of sum()

SystemVerilog

SystemVerilog , constraint-randomization , array-reduction-methods

1

18

July 1, 2026

Determining the bit width of operands in constraint

SystemVerilog

constraint-randomization , Evaluating-a-Constraint-expression , Size-Cast , Constraint-Expression

4

40

July 1, 2026

Assignment rules for different width & sign

SystemVerilog

SystemVerilog , signed , casting , assignment

5

24

July 1, 2026

What are the biggest pain points in simulation debugging for DV engineers?

UVM

SystemVerilog

2

32

July 1, 2026

Monitor-to-Scoreboard Connection

UVM

3

32

July 1, 2026

Difference between put_port and get_port?

UVM

UVM , put_port

8

2468

June 30, 2026

Why are UVM User-Defined Phase Classes Implemented as Singletons?

UVM

1

26

June 29, 2026

[SVA Question] Signal 'b' has to toggle only once within 10cycle window of signal 'a' after 'a' is asserted

SystemVerilog

assertion , SVA , SVA-Assertion

7

137

June 28, 2026

Unclear scheduling semantics for a flip-flop model with assign/deassign

SystemVerilog

4

30

June 27, 2026

Doing some academic research on AI for chip design. Would anyone be willing to share their experience.

SystemVerilog

1

32

June 26, 2026

Clarification regarding task run_phase() in UVM

UVM

1

21

June 26, 2026

implement a reference counter

UVM

3

38

June 25, 2026

Where to implement memory read/write operations in UVM agent when observing packet transactions in monitor?

UVM

3

56

June 23, 2026

Using uvm field automation macros in uvm_object extended types

UVM

UVM , uvm_config_db , field-macros

3

31

June 23, 2026

Terminology related to the formal tool

SystemVerilog

assertion

0

24

June 23, 2026

Understanding Array Reduction methods

SystemVerilog

constraint-arraysum , array-reduction-methods

10

111

June 18, 2026

QCX not activating with optimized UVM testbench (qsim only, no qopt -qcx license)

Coverage

UVM , Coverage

2

20

June 17, 2026

Using uvm_config_db::get(null, ...) Inside a UVM Sequence (uvm_object)

UVM

2

45

June 15, 2026

Uvm_config_db set in the below example correct?

UVM

1

108

June 15, 2026

UVM Field Macros - Positive flag

UVM

1

30

June 15, 2026

Layered Protocol Response Mechanism

UVM

get_response

0

36

June 15, 2026

Assertion not triggering for Asynchronous FIFO

SystemVerilog

assertion

1

35

June 15, 2026

Constraint 2d array using SUM operator

SystemVerilog

SystemVerilog , constraint

0

54

June 15, 2026

UVM Driver Communication: get_next_item()/item_done() vs get()/put() — Which is Preferred in Industry?

UVM

5

66

June 14, 2026

Constraint for memories

SystemVerilog

SystemVerilog , constraints

9

6595

June 13, 2026

Random Non overlapping Address (Memory allocator)

SystemVerilog

3

6450

June 13, 2026

Return value of pack() and unpack()

UVM

1

32

June 12, 2026