Verification Academy

Topic	Replies	Views	Activity
Welcome to our Verification Academy community! Announcements	0	814	December 27, 2022
Need help writing Systemverilog assertion (SVA) with req, busy, gnt SystemVerilog SystemVerilog , SVA-Assertion	8	25	October 1, 2026
UVM Test is not comming out UVM UVM	20	19953	September 30, 2026
What is the output of the tlm_fifo model? UVM UVM , TLM-FIFO-related	2	1260	September 30, 2026
Excluding the already defined bins Coverage SystemVerilog , Coverage , Dave-Rich	6	212	September 29, 2026
UVM_WARNING : map 'reg_map' does not seem to be initialized correctly, check that the top register model is locked() UVM	0	13	September 29, 2026
Confusion on calling SV system task $size for dynamic types SystemVerilog SystemVerilog , system-task , size	2	103	September 25, 2026
Question Regarding Hierarchical References SystemVerilog	4	52	September 23, 2026
Constraining leaf elements of 2D Array of handle SystemVerilog	3	39	September 23, 2026
UVM macro UVM UVM	5	1275	September 23, 2026
SystemVerilog reason of not putting always in program block SystemVerilog SystemVerilog	4	184	September 22, 2026
The Whys of UVM UVM UVM	7	6068	September 18, 2026
How to create, config, and use Agentic IA in a UVM-based Testbench? UVM SystemVerilog , UVM , Agentic-IA	0	86	September 14, 2026
What is Z-to-X conversion? Issue while trying to run assertions with Z values SystemVerilog SystemVerilog , assertion , SVA , Formal-Verification	0	58	September 14, 2026
Are class object handles passed by reference when used are class method arguments? SystemVerilog SystemVerilog	8	1504	September 14, 2026
Clocking event in Concurrent Assertions SystemVerilog SystemVerilog , assertion , SVA , Clocking-event-sva	2	110	September 9, 2026
Lifespan of memory of objects created during run_phase UVM UVM , UVM-MEMORY-MODELING , uvm_object	3	106	September 8, 2026
How do you evaluate AI tools for UVM/DV work? UVM UVM	0	81	September 7, 2026
Non integral expressions SystemVerilog SystemVerilog	8	2183	September 1, 2026
Chained range constraints in SystemVerilog SystemVerilog constraint-randomization , constriant	3	74	August 31, 2026
Difference between switch,crossbar and Interconnect UVM	1	76	August 31, 2026
Clocking Block default output skew not applied to output signal in Vivado Simulator 2018.x SystemVerilog Xilinx , Vivado , FPGA	2	70	August 29, 2026
Detection of Interrupt in Monitor UVM UVM , virtual-interface , rose	7	261	August 28, 2026
Valid expression types in the with clause SystemVerilog SystemVerilog , array-reduction-methods , with-clause	4	150	August 26, 2026
Unexpected Behaviour From Xilinx Vivado? SystemVerilog SystemVerilog	1	68	August 24, 2026
Class :final TopPacket extends LinkedPacket; SystemVerilog SystemVerilog	4	90	August 18, 2026
How to generate wlf using qrun command SystemVerilog	1	55	August 17, 2026
What happen if the antecedent occurs or it is true, but the consequent will never occur? SystemVerilog SVA	6	115	August 16, 2026
Preparing test plan for SPI protocol in UVM UVM UVM , SPI , SPI-protocol , SPI-Test-Plan , UVM-SPI-testbench	5	3363	August 13, 2026
Debugging VIP's API calls SystemVerilog SystemVerilog , Polymorphism	1	115	August 3, 2026