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Welcome to our Verification Academy community!
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1
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663
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September 13, 2023
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Once a certain sequence occurs that another seq shouldn't occur till simulation ends
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7
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582
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November 2, 2025
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restricting sequence as long as one variable is asserted
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4
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17
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November 2, 2025
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Default value of enumarated varaible is first value of enum
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4
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30
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November 1, 2025
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difference b/w nexttime and ##1
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1
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12
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October 31, 2025
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Migrating from IP to sub-system level
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1
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23
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October 31, 2025
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Why ref bit and int doesnt Work in sampling but int andref bit Does
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0
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10
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October 31, 2025
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Vertical re-use (from block to sub-system/chip level)
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4
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3268
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October 30, 2025
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Paper: Understanding SVA Degeneracy
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9
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530
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October 29, 2025
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In my design, I have an assign statement like assign var = (a == b) ? 1 : 0;. During simulation, var takes both values 1 and 0 as expected, but in Questa code coverage, this statement is still shown as not covered. Why is this happening?
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2
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12
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October 29, 2025
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SVA with multiple Implication operators
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0
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23
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October 29, 2025
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Why uvm_object_registry is called as lightweight proxy?
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1
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29
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October 28, 2025
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Function inside constraint
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1
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42
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October 28, 2025
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UVM Class Hierarchy ? can any one help me by giving me the full uvm base class hierarchy structure
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5
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30
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October 27, 2025
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is $fell(sig_a) true when sig_a from x to 0?
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1
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23
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October 27, 2025
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Question regarding latch behaviour
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1
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29
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October 27, 2025
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Question on use of RAL model for System-On-Chip verification
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4
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51
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October 24, 2025
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Multiple analysis ports to single implementation
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8
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106
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October 23, 2025
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Understanding the throughout SVA
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11
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1031
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October 20, 2025
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How to properly extend a test case from different parents
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2
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63
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October 21, 2025
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How to deep copy UVM transaction containing queue of objects?
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3
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37
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October 21, 2025
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SV assertion related to req and grant
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2
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51
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October 18, 2025
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Is there an alternative to sum() Constraint
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5
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1842
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October 19, 2025
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Difference between -> and => in assertions
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5
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140
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October 19, 2025
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How to use multiple sequences to override base test
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14
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153
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October 17, 2025
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QuestaSim not loading design after restart -f
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2
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19
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October 17, 2025
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What operators constitute a multi-threaded sequence
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1
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53
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October 16, 2025
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Config db fatal isssue
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1
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30
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October 16, 2025
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Clarification on sequence execution flow UVM cookbook figure
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6
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41
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October 16, 2025
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$xm_force isnt working to force tb signals using hierarchical paths
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2
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24
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October 16, 2025
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