Verification Academy

Topic	Replies	Views	Activity
Welcome to our Verification Academy community! Announcements	1	700	September 13, 2023
Randomization of req signal in priority arbiter SystemVerilog constraint-randomization , Priority-arbiter	0	11	January 13, 2026
Verilog-AMS on Symphony does not appear to work properly. SystemVerilog	2	16	January 13, 2026
Full_case parallel_case concrete explanation needed SystemVerilog Case-statement-in-sv	2	31	January 12, 2026
Assertion question :- SystemVerilog SystemVerilog , assertion , System-Verilog , systemverilogassertionSVA	5	453	January 11, 2026
Constraint Pattern problem SystemVerilog constraint-randomization	5	51	January 10, 2026
SystemVerilog constraint: unique addr across array of structs without auxiliary array SystemVerilog SystemVerilog , constraint-randomization , unique	3	59	January 9, 2026
How SV handles the execution of functions SystemVerilog	1	23	January 9, 2026
Requesting clarity on constraint solving SystemVerilog constraint-randomization	2	37	January 7, 2026
AHB Lite protocol Verification UVM SystemVerilog , UVM , Coverage , assertion	2	565	January 7, 2026
Working of uvm_cmdline_processor::get_arg_matches UVM UVM , uvm_cmdline_processor , get_arg_matches	3	33	January 6, 2026
Query on generating rand 2D array with sum of set bits equal to specific value and bits must be connected to each other SystemVerilog constraint-randomization , 2Darray	4	92	January 5, 2026
Assertion error SystemVerilog SystemVerilog , UVM , assertion , SVA	3	25	January 5, 2026
Using interface in testbench and for modules connection SystemVerilog virtual-interface , interface , Clocking-Block	1	18	January 5, 2026
Uvm_hdl_read gives Incorrect value UVM	3	81	January 4, 2026
Weighted constraints not working SystemVerilog constraint-randomization	3	44	January 2, 2026
Assertion calculation after reset SystemVerilog assertion , SVA	0	27	January 2, 2026
Sequence which admits : No match v/s Hard Zero SystemVerilog SystemVerilog , assertion , SVA	8	399	December 27, 2023
System verilog Assertion SystemVerilog assertion	4	70	January 1, 2026
Requesting clarity on intermediate signals in the sequences SystemVerilog assertion	2	43	January 1, 2026
Difference between below 2 sequences? SystemVerilog assertion	1	39	December 31, 2025
Advantage of TLM fifo over a mailbox OVM OVM	5	19599	December 29, 2025
Semaphore put method question SystemVerilog SystemVerilog , System-Verilog , semaphore-keys , semaphore-with-multiple-keys	5	413	December 28, 2025
Deleting elements returned via Array locator methods SystemVerilog unpacked-array , 2Darray , Aray-locator-methods	1	30	December 28, 2025
Time does not strictly flow forward SystemVerilog	3	81	December 27, 2025
Execution of action block in Abort properties (reject_on / accept_on) SystemVerilog assertion , SVA , reject_on , Action-block	3	44	December 27, 2025
Confusion with the master monitor and slave monitor functionality UVM UVM , SPI-Test-Plan	3	65	December 22, 2025
Displaying associative array elements in Specific order SystemVerilog accessing-the-associative-array-elements , associative-array-methods , associative_arrays	2	50	December 18, 2025
UVM 1.2 new warning - a resource with meta characters in the field name has been created UVM UVM , uvm_reg_block , Resource_db , UVMRSRCNOREGEX , UVM-12 , uvm-warning	12	7292	December 18, 2025
SVA to check a N-stage synchronizer output SystemVerilog SystemVerilog , assertion , System-Verilog , SVA , SVA-Assertion	9	68	December 18, 2025