Verification Academy

Topic	Replies	Views	Activity
Welcome to our Verification Academy community! Announcements	0	786	December 27, 2022
Detection of Interrupt in Monitor UVM UVM , virtual-interface , rose	2	44	August 4, 2026
Debugging VIP's API calls SystemVerilog SystemVerilog , Polymorphism	1	34	August 3, 2026
Merits of Overriding Sequence Items UVM UVM , Cookbook-SequencesOverrides	3	731	August 3, 2026
Sva and ai with rag rules SystemVerilog	1	78	July 27, 2026
Question on UVM Phases UVM UVM , UVM-phases , uvm_phases	1	53	July 24, 2026
What is the difference between uvm_config_db and uvm_resource_db? UVM UVM , uvm_config	22	43697	July 21, 2026
Type v/s Size cast within with clause of sum() SystemVerilog SystemVerilog , constraint-randomization , array-reduction-methods	5	100	July 15, 2026
is $fell(sig_a) true when sig_a from x to 0? SystemVerilog assertion , SVA	4	174	July 13, 2026
The question of disable SystemVerilog	6	69	July 13, 2026
Why create method is not part of uvm_object_wrapper? UVM uvm-factory	3	101	July 10, 2026
Resulting sign and bit length using Conditional Operator SystemVerilog SystemVerilog , Conditional-Operator , Ternary-Operator	4	74	July 9, 2026
DisplayPort Protocol (version 1.4) UVM Spec-Clarification	0	68	July 7, 2026
The difference between a looped `fork...join_none` and a serial `fork...join_none` SystemVerilog	5	73	July 7, 2026
Questions about the usage of Pattern Matching Conditional Statements SystemVerilog	3	67	July 6, 2026
How do we integrate the toolchain with uvm? UVM SystemVerilog , UVM	1	63	July 2, 2026
Determining the bit width of operands in constraint SystemVerilog constraint-randomization , Evaluating-a-Constraint-expression , Size-Cast , Constraint-Expression	4	76	July 1, 2026
Assignment rules for different width & sign SystemVerilog SystemVerilog , signed , casting , assignment	5	58	July 1, 2026
What are the biggest pain points in simulation debugging for DV engineers? UVM SystemVerilog	2	71	July 1, 2026
Monitor-to-Scoreboard Connection UVM UVM	3	124	July 1, 2026
Difference between put_port and get_port? UVM UVM , put_port	8	2498	June 30, 2026
Why are UVM User-Defined Phase Classes Implemented as Singletons? UVM UVM	1	64	June 29, 2026
[SVA Question] Signal 'b' has to toggle only once within 10cycle window of signal 'a' after 'a' is asserted SystemVerilog assertion , SVA , SVA-Assertion	7	172	June 28, 2026
Unclear scheduling semantics for a flip-flop model with assign/deassign SystemVerilog SystemVerilog	4	49	June 27, 2026
Doing some academic research on AI for chip design. Would anyone be willing to share their experience. SystemVerilog	1	47	June 26, 2026
Clarification regarding task run_phase() in UVM UVM	1	39	June 26, 2026
implement a reference counter UVM UVM	3	64	June 25, 2026
Where to implement memory read/write operations in UVM agent when observing packet transactions in monitor? UVM UVM	3	81	June 23, 2026
Using uvm field automation macros in uvm_object extended types UVM UVM , uvm_config_db , field-macros	3	40	June 23, 2026
Terminology related to the formal tool SystemVerilog assertion	0	33	June 23, 2026