Verification Academy

Topic	Replies	Views	Activity
Welcome to our Verification Academy community! Announcements	0	824	December 27, 2022
static functions, does the implicit return variable get overwritten by exp in return exp;? SystemVerilog	1	15	October 29, 2026
Adding virtual qualifier to predefined SV Functions SystemVerilog virtual-function , pre_randomize , post_randomize	1	10	October 29, 2026
Suggestions for basic SystemVerilog/UVM projects for freshers UVM	1	63	October 21, 2026
Unexpected Behaviour From Xilinx Vivado? SystemVerilog SystemVerilog	4	119	October 19, 2026
Use run_phase in scoreboard UVM SystemVerilog , UVM	1	88	October 14, 2026
Queries on Constrain Randomization SystemVerilog constraint-randomization , randomization	4	149	October 10, 2026
UVMF 2023.4_2 examples UVM UVMF	0	83	October 5, 2026
Need help writing Systemverilog assertion (SVA) with req, busy, gnt SystemVerilog SystemVerilog , SVA-Assertion	8	109	October 1, 2026
UVM Test is not comming out UVM UVM	20	20018	September 30, 2026
What is the output of the tlm_fifo model? UVM UVM , TLM-FIFO-related	2	1293	September 30, 2026
Excluding the already defined bins Coverage SystemVerilog , Coverage , Dave-Rich	6	247	September 29, 2026
UVM_WARNING : map 'reg_map' does not seem to be initialized correctly, check that the top register model is locked() UVM	0	47	September 29, 2026
Confusion on calling SV system task $size for dynamic types SystemVerilog SystemVerilog , system-task , size	2	140	September 25, 2026
Question Regarding Hierarchical References SystemVerilog	4	94	September 23, 2026
Constraining leaf elements of 2D Array of handle SystemVerilog	3	81	September 23, 2026
UVM macro UVM UVM	5	1309	September 23, 2026
SystemVerilog reason of not putting always in program block SystemVerilog SystemVerilog	4	211	September 22, 2026
The Whys of UVM UVM UVM	7	6119	September 18, 2026
How to create, config, and use Agentic IA in a UVM-based Testbench? UVM SystemVerilog , UVM , Agentic-IA	0	127	September 14, 2026
What is Z-to-X conversion? Issue while trying to run assertions with Z values SystemVerilog SystemVerilog , assertion , SVA , Formal-Verification	0	94	September 14, 2026
Are class object handles passed by reference when used are class method arguments? SystemVerilog SystemVerilog	8	1536	September 14, 2026
Clocking event in Concurrent Assertions SystemVerilog SystemVerilog , assertion , SVA , Clocking-event-sva	2	142	September 9, 2026
Lifespan of memory of objects created during run_phase UVM UVM , UVM-MEMORY-MODELING , uvm_object	3	133	September 8, 2026
How do you evaluate AI tools for UVM/DV work? UVM UVM	0	115	September 7, 2026
Non integral expressions SystemVerilog SystemVerilog	8	2230	September 1, 2026
Chained range constraints in SystemVerilog SystemVerilog constraint-randomization , constriant	3	94	August 31, 2026
Difference between switch,crossbar and Interconnect UVM	1	100	August 31, 2026
Clocking Block default output skew not applied to output signal in Vivado Simulator 2018.x SystemVerilog Xilinx , Vivado , FPGA	2	85	August 29, 2026
Detection of Interrupt in Monitor UVM UVM , virtual-interface , rose	7	282	August 28, 2026