[Interview Question] Writing a monitor for a given scenario below

UVM
1

The question is as follows -
Write a monitor for a scenario of a serial 4 bit wide signal being received from the interface output. The condition is that the payload which we will send from monitor to scoreboard(via Analysis port) will be in the following format -

ABCD______<Payload>______CAFE

Condition is -

  1. Once you receive ABCD continuously from output this will start the payload data to come and will continue till I receive CAFE if 4 nibbles continuously.

Please use signals as you wish for writing the driver run phase.

2

That’s not a question–it’s an assignment. Please make an attempt and then we can guide you.

3

Hi Dave!
This was the code I wrote. Can you point me it’s limitations or if I am missing something

class serial_monitor extends uvm_monitor;
  `uvm_component_utils(serial_monitor)
  
  uvm_analysis_port #(transaction) analysis_port;
  
  virtual serial_if vif;
  function new(string name, uvm_component parent);
    super.new(name,parent);
    analysis_port = new("analysis_port", this);
  endfunction
  
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    if(!uvm_config_db#(virtual serial_if)::get(this,"","vif",vif))
      `uvm_fatal("get_type_name()","couldnt get interface");
  endfunction
  
  task run_phase(uvm_phase phase);
    transaction payload;
    bit[15:0] shift_reg = 16'h0000;
    bit capture = 0;
    
    forever begin
      @(posedge vif.clk)
      shift_reg = {shift_reg[11:0], vif.data};
      if(shift_reg == 16'hABCD)
        begin
          capture = 1;
          payload = 4'b0;
          $display("DETECTED SEQ START CONDITION");
        end
      if(capture ==1)
        begin
          ##1
          payload = {payload, vif.data};
        end
      
      if(shift_reg == 16'CAFE && capture)
        begin
          capture = 0;
          analysis_port.write(payload);
          $display("Payload sent to Scroeboard, waiting for next");
        end
      
    end
  endtask
4

I have posted the solution below, I wanted to make sure there is nothing wrong w.r.t. to clock cycle sampling i.e. if there is any miss regarding to sampling at wrong timing. Also any additional input you think that may improve this piece of code.

5

Any limits on the size of the payload?
And after you send the first payload, you need to clear out the shift register.

6

Hi Dave, payload is supposed to be 16bit in size.