Topics tagged analysis-port

Topic	Replies	Views	Activity
Multiple analysis ports to single implementation UVM SystemVerilog , UVM , analysis-port	8	110	October 23, 2025
Connection between multiple analysis port to single analysis import UVM UVM , analysis-port , analysis-export	6	3083	February 18, 2025
On monitor and scoreboard connection UVM analysis-port	1	144	August 6, 2024
Analysis Port Write functionality UVM analysis-port , analysis-export	1	385	April 30, 2024
2 process writing on an analysis port from monitor UVM UVM , analysis-port , UVM-monitor , uvm_monitor-uvm_scoreboard-write	11	1195	March 18, 2024
Guidelines for using analysis port in monitor SystemVerilog SystemVerilog , UVM , analysis-port , UVM-monitor	3	1529	June 30, 2021
Connecting Sequence to Scoreboard UVM UVM , sequence , analysis-port , UVM-scoreboard	6	3788	August 10, 2020
Monitor scoreboard Error UVM UVM , analysis-port , UVM-monitor , UVM-scoreboard-problem , systemverilog-uvm	4	1437	March 12, 2020
Usage of pair_ap from uvm_in_order_comparator UVM UVM , tlm , analysis-port , comparator , Component-construction	2	1284	August 14, 2019
UVM_DRIVER- Driving an interface at an event UVM SystemVerilog , UVM , analysis-port , System-Veriilog-Events	1	1936	March 8, 2019
Overhead of calling analysis port write() method UVM UVM , analysis-port	2	1739	August 29, 2018
Where to use ports and analysis ports UVM UVM , analysis-port	6	1173	August 1, 2018
Getting same item from analysis fifo, even though monitor writes only once UVM UVM , analysis-port	4	1737	March 27, 2018
Whats the difference between hierarchical exports direct assignment and hierarchical exports assign through connect? UVM UVM , hierarchical , analysis-port	1	1309	January 3, 2018
Configuring driver-sequencer used, from environment? UVM UVM , analysis-port , driver-callback	5	1784	May 19, 2017
Can we get transaction in Functional Coverage through multiple Analysis Ports in Scoreboard? Coverage Coverage , scoreboard , functional-coverage , analysis-port	1	1729	March 25, 2017
Can I have an analysis port inside my driver ?If yes, then why we have monitor ?If no,why? UVM UVM , analysis-port	3	3522	August 30, 2016
If I do not connect uvm_analysis_port to uvm_analysis_imp and use uvm_analysis_port.write method. What should happen UVM UVM , Write , FATAL-ERROR , analysis-port , connect_phase-in-uvm	3	1873	January 25, 2016
UVM analysis port UVM UVM , analysis-port	3	1901	December 23, 2015
About the analysis port "write" function implementation UVM UVM , analysis-port , UVM-TLM-Analysis-port , Cookbook-Analysis	2	6194	April 11, 2015
Failing to connect analysis port UVM UVM , sequencer , uvm_analysis_imp , analysis-port	4	2089	April 18, 2014
Can we use ports in driver, inside driver callback method driver's handle? UVM UVM , UVM-callback , analysis-port	7	2848	March 18, 2014

Multiple analysis ports to single implementation

UVM

SystemVerilog , UVM , analysis-port

8

110

October 23, 2025

Connection between multiple analysis port to single analysis import

UVM

UVM , analysis-port , analysis-export

6

3083

February 18, 2025

On monitor and scoreboard connection

UVM

analysis-port

1

144

August 6, 2024

Analysis Port Write functionality

UVM

analysis-port , analysis-export

1

385

April 30, 2024

2 process writing on an analysis port from monitor

UVM

UVM , analysis-port , UVM-monitor , uvm_monitor-uvm_scoreboard-write

11

1195

March 18, 2024

Guidelines for using analysis port in monitor

SystemVerilog

SystemVerilog , UVM , analysis-port , UVM-monitor

3

1529

June 30, 2021

Connecting Sequence to Scoreboard

UVM

UVM , sequence , analysis-port , UVM-scoreboard

6

3788

August 10, 2020

Monitor scoreboard Error

UVM

UVM , analysis-port , UVM-monitor , UVM-scoreboard-problem , systemverilog-uvm

4

1437

March 12, 2020

Usage of pair_ap from uvm_in_order_comparator

UVM

UVM , tlm , analysis-port , comparator , Component-construction

2

1284

August 14, 2019

UVM_DRIVER- Driving an interface at an event

UVM

SystemVerilog , UVM , analysis-port , System-Veriilog-Events

1

1936

March 8, 2019

Overhead of calling analysis port write() method

UVM

UVM , analysis-port

2

1739

August 29, 2018

Where to use ports and analysis ports

UVM

UVM , analysis-port

6

1173

August 1, 2018

Getting same item from analysis fifo, even though monitor writes only once

UVM

UVM , analysis-port

4

1737

March 27, 2018

Whats the difference between hierarchical exports direct assignment and hierarchical exports assign through connect?

UVM

UVM , hierarchical , analysis-port

1

1309

January 3, 2018

Configuring driver-sequencer used, from environment?

UVM

UVM , analysis-port , driver-callback

5

1784

May 19, 2017

Can we get transaction in Functional Coverage through multiple Analysis Ports in Scoreboard?

Coverage

Coverage , scoreboard , functional-coverage , analysis-port

1

1729

March 25, 2017

Can I have an analysis port inside my driver ?If yes, then why we have monitor ?If no,why?

UVM

UVM , analysis-port

3

3522

August 30, 2016

If I do not connect uvm_analysis_port to uvm_analysis_imp and use uvm_analysis_port.write method. What should happen

UVM

UVM , Write , FATAL-ERROR , analysis-port , connect_phase-in-uvm

3

1873

January 25, 2016

UVM analysis port

UVM

UVM , analysis-port

3

1901

December 23, 2015

About the analysis port "write" function implementation

UVM

UVM , analysis-port , UVM-TLM-Analysis-port , Cookbook-Analysis

2

6194

April 11, 2015

Failing to connect analysis port

UVM

UVM , sequencer , uvm_analysis_imp , analysis-port

4

2089

April 18, 2014

Can we use ports in driver, inside driver callback method driver's handle?

UVM

UVM , UVM-callback , analysis-port

7

2848

March 18, 2014