Analysis Port Write functionality

UVM
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1

How does write work for an analysis port?

I had some code that I wrote that looked like the following:

(note that m_predictor_ssi_ap is eventually connected to a fifo in my comparator so what I want to see is the reference transactions stacked in groups of 4 )

uvm_analysis_port #(some_seq_item) m_predictor_ssi_ap;
m_predictor_ssi_ap = new("m_predictor_ssi_ap", this);

some_seq_item ref_trans_ssi;
ref_trans_ssi = some_seq_item::type_id::create("ref_trans_ssi");


for(int i=0; i<4; i++) begin
 //some code that sets ref_trans_ssi 
//(each iteration of loop can have a different value for ref_trans_ssi)
//The iteration is also passed as well so the comparators know which "i" is sent
  m_predictor_ssi_ap.write(ref_trans_ssi);

end

And here I saw that in my fifo I would only get the last value of ref_trans_ssi (that is the value of ref_trans_ssi when i=3)

But when I move ref_trans_ssi = some_seq_item::type_id::create("ref_trans_ssi"); inside the for loop I see separate seq_items being sent.

My questions are:

  1. Is write doing a pass by reference? If so I get why the first method doesn’t work since I’m overwriting the value
  2. If write is doing a pass by reference then why does ref_trans_ssi = some_seq_item::type_id::create("ref_trans_ssi"); within the loop work? Am I not naming consecutive sequence items with the same name (ref_trans_ssi)? Or is there something going on under-the-hood that ensures they are different objects.

Thanks!

2

write() copies its argument by value. That value is a handle to a class object. Class objects are always accessed by a reference using the handle value.

create() constructs a new class object, returning a unique handle that references that object. The UVM string name does not need to be unique in this case.

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