Uvm build phase

In uvm,

virtual function void build_phase(uvm_phase phase);
      super.build_phase(phase);  // Calls my_monitor's build_phase first
      $display("Building my_custom_monitor with additional setup...");
      // Custom behavior for this specific monitor
   endfunction
endclass

why we mentioning build_phase as virtual?
In uvm base class, build_phase is virtual,so that it is intended to be overridden in the custom uvm class. But again in custom class also why it is need to give a virtual keyword in build_phase?

In SystemVerilog, if the base class declares a method virtual, the method is always virtual in all derived subclasses. The virtual keyword is optional.