I’m trying to verify the functionality of single port ram and not getting the data_out as expected , im only getting the value of data_in on data_out at the clock cycle when write_en goes low and all previous values are missed.
ram module -
module single_port_ram (
input logic clk ,
// input logic reset ,
input logic write_en ,
input logic [7:0] data_in ,
input logic [4:0] addr ,
output logic [7:0] data_out
);
logic [7:0] ram [32];
logic [4:0] temp;
always_ff @(posedge clk ) begin
if (write_en)
ram[addr] <=data_in;
else
temp<=ram[addr];
end
assign data_out = temp;
endmodule
testbench code -
module tb;
logic clk ;
// logic reset ;
logic write_en ;
logic [7:0] data_in ;
logic [4:0] addr ;
logic [7:0] data_out ;
logic [7:0] data_q[$] ;
logic [7:0] data;
single_port_ram dut (.clk(clk), .write_en(write_en) , .data_in(data_in) , .addr(addr) , .data_out(data_out));
always #10 clk= ~clk;
initial begin
clk =0;
/*
reset = 1'b1 ;
#20;
reset = 1'b0;
*/
end
initial begin
repeat(5) begin
@(posedge clk ) write_en = 1;
addr=$urandom();
data_in = $urandom();
data_q.push_back(data_in);
end
repeat(5) begin
@(posedge clk) write_en = 1'b0;
data = data_q.pop_front();
if(data_out!=data) $display ("comparison failed");
else
$display ("pass");
end
repeat(5) begin
@(posedge clk) write_en = 1'b1;
addr=$urandom();
data_in = $urandom();
data_q.push_back(data_in);
end
repeat(5) begin
@(posedge clk) write_en = 1'b0;
data = data_q.pop_front();
if(data_out!=data) $display("comparison failed") ;
else
$display("pass");
end
end
initial begin
$dumpfile("dump.vcd");
$dumpvars();
end
initial begin
#500 ;
$finish();
end
endmodule
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