Can anyone suggest how to write following assertion

SystemVerilog
,
1

When the REQ is asserted, The GRANT signal should be asserted after 3 clock cycles. The GRANT signal must remain high for the same no.of clock cycles as the REQ signal.
Ex: If the REQ signal is high for 3 cycles, the GRANT signal should be asserted for after 3cycles and remain high for 3 cycles.
Similarly, If the REQ signal is high for 4 cycles, the GRANT signal should be asserted for after 3cycles and remain high for 4 cycles.
I tried this, is it correct way ? please suggest
$rose(REQ) |-> ##3 $rose(GRANT)##0 ($stable(GRANT) throughout REQ)

2

@Deep_learn_R
You asked this question already
Solve the following assertion - SystemVerilog - Verification Academy

Have you tested your code ? Did the output match your expectations ?

3

Not matching

4

So this answers your original question “is it correct way ?”
Now try using my suggestion in your previous thread

5

Try this,

Sequence S1;
req |-> ##3 gnt ;
endsequence

property p1;
(s1 intersect 1’b1)[*4:$] //min 4 I took to take care when request is asserted for 1 cycle
endproperty

assert property(@(posedge clk) p1);