When the REQ is asserted, The GRANT signal should be asserted after 3 clock cycles. The GRANT signal must remain high for the same no.of clock cycles as the REQ signal.
Ex: If the REQ signal is high for 3 cycles, the GRANT signal should be asserted for after 3cycles and remain high for 3 cycles.
Similarly, If the REQ signal is high for 4 cycles, the GRANT signal should be asserted for after 3cycles and remain high for 4 cycles.
I tried this, is it correct way ? please suggest
$rose(REQ) |-> ##3 $rose(GRANT)##0 ($stable(GRANT) throughout REQ)
@Deep_learn_R
You asked this question already
Solve the following assertion - SystemVerilog - Verification Academy
Have you tested your code ? Did the output match your expectations ?
Not matching
So this answers your original question “is it correct way ?”
Now try using my suggestion in your previous thread
Try this,
Sequence S1;
req |-> ##3 gnt ;
endsequence
property p1;
(s1 intersect 1’b1)[*4:$] //min 4 I took to take care when request is asserted for 1 cycle
endproperty
assert property(@(posedge clk) p1);
Had you tried running this coding personally you would have noticed that the code doesn’t even compile !!
That is excluding that it should be ::
(1) sequence S1 and not Sequence S1
(2) ( S1 intersect 1’b1 )[*4:$] and not ( s1 intersect 1’b1)[*4:$]
You need to revisit your SVA basics
Also note that intersect operator requires both lhs & rhs sequence start at the same clock as well as end at the same clock.
Your rhs sequence is of 1 clock length whereas lhs sequence is more than 1 clock.
As a result intersect operator will fail at every clock